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Freesclae KL25黑色的那块开发板
用UART0可以实现DMA方式的发送
但是UART1不行，请问在设置UART0和UART1的时候有什么不同点呢？
下面是代码，请大神帮忙看一下
//====================UART初始化===============================
if (COM1==comX)
{
#ifndef USE_UART1_DMA_FT
ASSERT(0);
#endif
// Enable Uart1 Clock
SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
if (PTE0 == UART1_TX_PORT)
{// Enable the UART_TXD function on PTE0
PORTE_PCR0 = PORT_PCR_MUX(0x3);
}
if (PTE1 == UART1_RX_PORT)
{// Enable the UART_RXD function on PTE1
PORTE_PCR1 = PORT_PCR_MUX(0x3);
}
}
else
{
#ifndef USE_UART2_DMA_FT
ASSERT(0);
#endif
// Enable Uart2 Clock
SIM_SCGC4 |= SIM_SCGC4_UART2_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
if (PTD3 == UART2_TX_PORT)
{// Enable the UART_TXD function on PTD3
PORTD_PCR3 = PORT_PCR_MUX(0x3);
}
if (PTD2 == UART2_RX_PORT)
{// Enable the UART_RXD function on PTD2
PORTD_PCR2 = PORT_PCR_MUX(0x3);
}
}
// Diable Uart1 Tx Rx
UART_C2_REG(m_uart_arr[comX]) &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
// Configure the uart for 8-bit mode, no parity
UART_C1_REG(m_uart_arr[comX]) = 0x00;
// Baundrate setting
l_sbr = (uint16_t)((periph_clk_khz*1000)/(boundRate * 16));
l_temp = UART_BDH_REG(m_uart_arr[comX]) & ~(UART_BDH_SBR(0x1F));
UART_BDH_REG(m_uart_arr[comX]) = l_temp | UART_BDH_SBR(((l_sbr & 0x1F00) >> 8));
UART_BDL_REG(m_uart_arr[comX]) = (uint8_t)(l_sbr & UART_BDL_SBR_MASK);
// Enable RX,IDLE Interrupt
UART_C2_REG(m_uart_arr[comX]) |= UART_C2_ILIE_MASK | UART_C2_RIE_MASK;
// Enable Uart1 DMA
UART_C4_REG(m_uart_arr[comX]) |= UART_C4_TDMAS_MASK;
enable_irq(UART0SE_irq_no+comX);
// Enable Tx & Rx
UART_C2_REG(m_uart_arr[comX]) |= (UART_C2_TE_MASK | UART_C2_RE_MASK);
//====================UART初始化===============================
//====================DMA初始化===============================
static void dma_init(Uart_Com_Typedef comX)
{
ASSERT(IS_UART_COM(comX));
// Enable dma clock
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
// Config DMA Mux for UART operation
// Disable DMA Mux channel
DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR, comX) &= ~DMAMUX_CHCFG_ENBL_MASK;
// Clear pending errors and/or the done bit
if (((DMA_DSR_BCR_REG(DMA_BASE_PTR, comX) & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
|| ((DMA_DSR_BCR_REG(DMA_BASE_PTR, comX) & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
|| ((DMA_DSR_BCR_REG(DMA_BASE_PTR, comX) & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
|| ((DMA_DSR_BCR_REG(DMA_BASE_PTR, comX) & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
{
DMA_DSR_BCR_REG(DMA_BASE_PTR, comX) |= DMA_DSR_BCR_DONE_MASK;
}
// Clear Source size and Destination size fields.
DMA_DCR_REG(DMA_BASE_PTR,comX) &= ~(DMA_DCR_SSIZE_MASK
| DMA_DCR_DSIZE_MASK
);
// Set DMA as follows:
// Source size is byte size
// Destination size is byte size
// D_REQ cleared automatically by hardware
// Destination address will be incremented after each transfer
// Cycle Steal mode
// External Requests are enabled
// Asynchronous DMA requests are enabled.
// Enable DMA Interrupt
DMA_DCR_REG(DMA_BASE_PTR,comX)|= (
DMA_DCR_SSIZE(1)
| DMA_DCR_DSIZE(1)
| DMA_DCR_SINC_MASK
| DMA_DCR_CS_MASK
// | DMA_DCR_ERQ_MASK
| DMA_DCR_EINT_MASK
);
// Set destination Address (this is the UARTx_D register)
if (COM0==comX)
{
DMA_DAR_REG(DMA_BASE_PTR,comX) = UART0_D_ADDRESS;
}
else if (COM1==comX)
{
DMA_DAR_REG(DMA_BASE_PTR,comX) = UART1_D_ADDRESS;
}
else
{
DMA_DAR_REG(DMA_BASE_PTR,comX) = UART2_D_ADDRESS;
}
// Set source address
DMA_SAR_REG(DMA_BASE_PTR,comX) = (uint32_t)&(m_uart_tx_buf[comX][0]);
// Select the DMA Channel Source
DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,comX) = 0x03+2*comX;
DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,comX) |= DMAMUX_CHCFG_ENBL_MASK;
// Enable DMA interrupt
enable_irq(DMA0_irq_no+comX);
}
//=================DMA初始化==================================
//=================发送==============================
uint8_t uart_send_data(Uart_Com_Typedef comX, uint8_t *pData, uint32_t len)
{
uint32_t i=0;
ASSERT(IS_UART_COM(comX) && pData && len>0 && len<UART_TXBUF_SIZE);
m_transmit_complete_flag[comX] = 0;
// Set BCR to know how many bytes to transfer
DMA_DSR_BCR(comX) = DMA_DSR_BCR_BCR(len);
memset(m_uart_tx_buf[comX], 0x00, sizeof(m_uart_tx_buf[comX]));
memcpy(m_uart_tx_buf[comX], pData, len);
// Enables the DMA channel
//DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR, comX) |= DMAMUX_CHCFG_ENBL_MASK;
DMA_DCR_REG(DMA_BASE_PTR,comX) |= DMA_DCR_ERQ_MASK;
while (i++<0xffffff && !m_transmit_complete_flag[comX]);
if (m_transmit_complete_flag[comX])
{
return len;
}
return 0;
}
//==========================================================
//================DMA中断======================================
void DMA1_IRQHandler(void)
{
// Clear pending errors or the done bit
if (((DMA_DSR_BCR1 & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
|| ((DMA_DSR_BCR1 & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
|| ((DMA_DSR_BCR1 & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
|| ((DMA_DSR_BCR1 & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
{
// Enable DMA1
DMA_DCR_REG(DMA_BASE_PTR,COM1) &= ~DMA_DCR_ERQ_MASK;
// Set source address
DMA_SAR_REG(DMA_BASE_PTR,COM1) = (uint32_t)&(m_uart_tx_buf[COM1][0]);
DMA_DSR_BCR1 |= DMA_DSR_BCR_DONE_MASK;
}
// Set transmit ok flag
m_transmit_complete_flag[COM1] = 1;
}
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阿莫论坛20周年了！感谢大家的支持与爱护！！
你熬了10碗粥，别人一桶水倒进去，淘走90碗，剩下10碗给你，你看似没亏，其实你那10碗已经没有之前的裹腹了，人家的一桶水换90碗，继续卖。说白了，通货膨胀就是，你的钱是挣来的，他的钱是印来的，掺和在一起，你的钱就贬值了。
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发表于 2015-2-11 15:29:23
楼主
