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发表于 2014-12-3 17:59:11
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本帖最后由 Link_Ling 于 2014-12-3 18:01 编辑
查了Altera 官网的论坛
http://www.alteraforum.com/forum/showthread.php?t=2892
http://www.alteraforum.com/forum/showthread.php?t=5927
http://www.alteraforum.com/forum/showthread.php?t=3649
All IO Pins of an unprogrammed device should be Tri-stated with a weak pull up. (cf. Cyclone II Handbook - Feb 08 - p. 1-3) So if you do not have a pull down at the pins you will see the pins go up to 3.3V.
The I/O are really tri-stated at power-up, reset, configuration and initialization (to be verified).
In cyclone II device, there are a weak pull-up resistors(~25kOhms) wich pull the pins high.
See datasheet and "configuration handbook"
得出结论在上电、配置期间,FPGA的IO默认是三态,且内部弱上拉,上拉电阻视VCCIO而定
cyclone handbook “Table 5-3 ” 有标出Rconf的值,如VCCIO=3.3V ,上拉电阻为25K
所以要使IO在上电、配置期间输出低,只有外部下拉电阻,“Table 5-3 ” 也给出了下拉电阻的推荐值1~2K
所以 3、5、6楼是正解!
PS: DEV_OE 可以研究一下下,貌似可以例外,不知道是所有Pin,还是可以指定某些Pin |
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