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楼主 |
发表于 2014-9-29 15:27:56
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你是说testbench这边吗？算了，我把我的文件传上来
testbench文件下面
`timescale 1ns/1ps
module para_to_seri_tb;
reg in_clk;
reg in_rest;
reg in_en;
reg [7:0] in_para_data;
wire out_seri_data;
always #5 in_clk=~in_clk;
initial
begin
in_rest=1'b0;
in_clk=1'b0;
#200 in_rest=1'b1;
in_para_data=8'b11001100;
end
reg[6:0] count;
always@(posedge in_clk or negedge in_rest)
if(!in_rest)
count<=7'b0;
else if(count>25)
count<=0;
else
count<=count+1;
always@(posedge in_clk or negedge in_rest)
if(!in_rest)
in_en<=1'b0;
else if(count==6||count==18)
in_en<=1'b1;
else
in_en<=1'b0;
para_to_seri u
(
.clk(in_clk),
.rest(in_rest),
.en(in_en),
.data_in(in_para_data),
.data_out(out_seri_data)
);
endmodule
被激励的文件
module para_to_seri(clk,rest,en,data_in,data_out);
input clk,rest,en;
input[7:0] data_in;
output data_out;
reg key1;
always@(posedge clk or negedge rest or negedge en)
if(!rest)
key1<=1'd0;
else if(!en)
key1<=en;
else
key1<=key1;
reg eadge_rise;
always@(posedge clk or negedge rest)
if(!rest)
eadge_rise<=1'b0;
else if(en&&!key1)
eadge_rise<=1'b1;
else
eadge_rise<=eadge_rise;
reg [3:0] count;
always@(posedge clk or negedge rest)
if(!rest)
count<=4'b0;
else if(eadge_rise==1)
count<=4'b0;
else if(count==4'd10)
count<=4'b0;
else
count<=count+1;
reg[7:0] buffer;
always@(posedge clk or negedge rest)
if(!rest)
buffer<=8'b0;
else if((count>1)&&(count<10))
buffer<={buffer[0],buffer[7:1]};
else if(count==4'd0)
buffer<=data_in;
else
buffer<=buffer;
assign data_out=buffer[0];
endmodule
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发表于 2014-9-29 14:42:56
