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本帖最后由 RAMILE 于 2014-9-27 13:54 编辑
这个电路的特点是每个灯的点亮时间独立可调,top模块里面,例化monostable模块时候,parameter参数控制延迟计数器的位数
- //--------------------------------
- module monostable
- (
- input clk,
- input trig,
- output testout2
- );
- parameter WIDTH = 10;
- reg state_in;
- reg state_ref;
- reg [(WIDTH-1):0]coutn_out;
- wire trig_gate;
- wire trig_out;
- wire carry;
- assign carry = coutn_out[WIDTH-1];
- assign trig_gate = testout2;
- assign trig_out = trig & trig_gate;
- assign testout = coutn_out[(WIDTH-1):0];
- assign testout2 = ( state_ref == state_in);
-
- always @(posedge trig )
- if(testout2)
- state_in = ~state_in;
- else
- state_in = state_in;
-
- always @(posedge clk)begin
- if(state_in != state_ref)
- coutn_out = coutn_out + 1'b1;
- else
- coutn_out = 0;
- end
-
- always @(posedge carry )
- state_ref <= ~state_ref;
-
- endmodule
- //-----------------------------------
- module div_count(
- input clk,
- output clk_div
- );
- parameter DIV_REG_WIDTH = 16;
- reg [(DIV_REG_WIDTH-1):0] count;
- assign clk_div = count[DIV_REG_WIDTH-1];
- always@(posedge clk)
- count <= count + 1;
- endmodule
- //================
- module top(
- input clk,
- input trig,
- output out1,
- output out2,
- output out3,
- output out4
- );
- wire in1,in2,in3,in4;
- assign in2 = out1;
- assign in3 = out2;
- assign in4 = out3;
- div_count div_count_i(.clk(clk), .clk_div(clk_solw));
- monostable #(12)monostable_i1(.clk(clk_solw), .trig(trig), .testout2(out1));
- monostable #(13)monostable_i2(.clk(clk_solw), .trig(in2), .testout2(out2));
- monostable #(11)monostable_i3(.clk(clk_solw), .trig(in3), .testout2(out3));
- monostable #(11)monostable_i4(.clk(clk_solw), .trig(in4), .testout2(out4));
- endmodule
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阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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