写了一个按键触发的流水灯，基于单稳态电路的

RAMILE

这个电路的特点是每个灯的点亮时间独立可调，top模块里面，例化monostable模块时候，parameter参数控制延迟计数器的位数

1. //--------------------------------
   
2. module monostable
   
3. (
   
4. input clk,
   
5. input trig,
   
6. output testout2
   
7. );
   
8. parameter WIDTH = 10;
   
9. reg state_in;
   
10. reg state_ref;
    
11. reg [(WIDTH-1):0]coutn_out;
    
12. 
    
13. wire trig_gate;
    
14. wire trig_out;
    
15. wire carry;
    
16. assign carry = coutn_out[WIDTH-1];
    
17. assign trig_gate = testout2;
    
18. assign trig_out = trig & trig_gate;
    
19. 
    
20. assign testout =  coutn_out[(WIDTH-1):0];
    
21. assign testout2 = ( state_ref == state_in);
    
22.        
    
23. always @(posedge trig  )
    
24.     if(testout2)
    
25.         state_in = ~state_in;
    
26.     else
    
27.         state_in =  state_in;
    
28.   
    
29. always @(posedge clk)begin
    
30.     if(state_in != state_ref)
    
31.         coutn_out  = coutn_out + 1'b1;
    
32.     else
    
33.         coutn_out = 0;
    
34. end                 
    
35. 
    
36. always @(posedge carry )
    
37.     state_ref <= ~state_ref;
    
38. 
    
39. endmodule
    
40. //-----------------------------------
    
41. 
    
42. module div_count(
    
43.     input clk,
    
44.     output clk_div
    
45. );
    
46. parameter DIV_REG_WIDTH = 16;
    
47. 
    
48. reg [(DIV_REG_WIDTH-1):0] count;
    
49. assign clk_div = count[DIV_REG_WIDTH-1];
    
50. 
    
51. always@(posedge clk)
    
52.     count <= count + 1;
    
53. 
    
54. endmodule
    
55. 
    
56. //================
    
57. module top(
    
58.     input clk,
    
59.     input trig,
    
60.     output out1,
    
61.     output out2,
    
62.     output out3,
    
63.     output out4
    
64. );
    
65. wire in1,in2,in3,in4;
    
66. 
    
67. assign in2 = out1;
    
68. assign in3 = out2;
    
69. assign in4 = out3;
    
70. 
    
71. div_count div_count_i(.clk(clk), .clk_div(clk_solw));
    
72. monostable #(12)monostable_i1(.clk(clk_solw), .trig(trig), .testout2(out1));
    
73. monostable #(13)monostable_i2(.clk(clk_solw), .trig(in2), .testout2(out2));
    
74. monostable #(11)monostable_i3(.clk(clk_solw), .trig(in3), .testout2(out3));
    
75. monostable #(11)monostable_i4(.clk(clk_solw), .trig(in4), .testout2(out4));
    
76. 
    
77. 
    
78. endmodule

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chinazhaoyl

谢谢分享!