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发表于 2014-5-2 09:52:24
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always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 3'd6; // Initial SDRam at first
C1 <= 11'd0;
C2 <= 5'd0;
Used <= 5'd0;
rStart <= 3'b000;
isStart <= 3'b000;
isInit <= 1'b0;
isBusy <= 1'b1;
isDone <= 1'b0;
end
else
case( i )
0: // IDLE state
if( C1 >= T15US ) begin C1 <= 11'd0; Used <= 5'd9; rStart <= 3'b100; i <= 3'd1; end
else if( RdEN_Sig ) begin C1 <= C1 + 1'b1; Used <= 5'd8; rStart <= 3'b010;i <= 3'd3; end
else if( WrEN_Sig ) begin C1 <= C1 + 1'b1; Used <= 5'd9; rStart <= 3'b001;i <= 3'd3; end
else begin C1 <= C1 + 1'b1; end
/***************************/
1: // Auto Refresh Done , 9 clock on this step
if( C2 == Used -1 ) begin C2 <= 5'd0; i <= i + 1'b1; end
else begin isStart <= rStart; C2 <= C2 + 1'b1; end
2: // 1 clock one this step
begin isStart <= 3'd0; C1 <= C1 + 1'b1; i <= 3'd0; end
/***************************/
3: // Read and Write Done
if( C2 == Used -1) begin C2 <= 5'd0; C1 <= C1 + Used; i <= i + 1'b1; end
else begin isStart <= rStart; C2 <= C2 + 1'b1; end
/***************************************/
4: // Generate Done Signal
begin isStart <= 3'd0; isDone <= 1'b1; C1 <= C1 + 1'b1; i <= i + 1'b1; end
5:
begin isDone <= 1'b0; C1 <= C1 + 1'b1; i <= 3'd0; end
/******************************************/
6: // Initial SDRam using 21 clock
if( Init_Done_Sig ) begin isBusy <= 1'b0; isInit <= 1'b0; C1 <= C1 + 1'b1; i <= 3'd0; end
else begin isBusy <= 1'b1; isInit <= 1'b1; end
/******************************************/
endcase
assign Func_Start_Sig = isStart;
/******************************************/
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 4'd0;
rCMD <= _NOP;
rBA <= 14'h3fff;
rDQM <= 2'b11;
rData <= 16'd0;
isOut <= 1'b1;
end
else if( Func_Start_Sig[2] )
case( i )
/*********************************/
0: // Send Auto Refresh Command
begin rCMD <= _AR; i <= i + 1'b1; end
1,2,3,4,5,6,7: // Send 7 nop Clk for tRFC-63
begin rCMD <= _NOP; i <= i + 1'b1; end
/*********************************/
8: // return i to 0
begin i <= 4'd0; end
/*************************************/
endcase
else if( Func_Start_Sig[1] )
case( i )
0: // Set IO to input state
begin isOut <= 1'b0; rData <= 16'd0; i <= i + 1'b1; end
1: // Send Active command with Bank and Row address
begin rCMD <= _ACT; rBA <= BRC_Addr[21:8]; i <= i + 1'b1; end
2: // Send 1 nop Clk for tRCD-20ns
begin rCMD <= _NOP; i <= i + 1'b1; end
/***************************************/
3: // Send Read command and column address, pull down DQM clock and pull up A10 to auto precharge.
begin rCMD <= _RD; rBA <= { BRC_Addr[21:20], 4'b0100, BRC_Addr[7:0]}; rDQM <= 2'b00; i <= i + 1'b1; end
4,5: // Send 2 nop Clk for CAS Latency
begin rCMD <= _NOP; rDQM <= 2'b11; i <= i + 1'b1; end
/******************************************/
6: // Read Data
begin rData <= SDRAM_DATA; i <= i + 1'b1; end
/******************************************/
7: // return i to 0
begin i <= 4'd0; end
/*******************************************/
endcase
else if( Func_Start_Sig[0] )
case( i )
/***************************************/
0: // Set IO to output State
begin isOut <= 1'b1; i <= i + 1'b1; end
1: // Send Active Command with Bank and Row address
begin rCMD <= _ACT; rBA <= BRC_Addr[21:8]; i <= i + 1'b1; end
2: // Send 1 nop Clk for tRCD-20ns
begin rCMD <= _NOP; i <= i + 1'b1; end
/*********************************************/
3: // Send Write command with row address, pull down DQM 1 clk and pull up A10 1 clk to Auto Precharge
begin rCMD <= _WR; rBA <= { BRC_Addr[21:20], 4'b0100, BRC_Addr[7:0] }; rDQM <= 2'b00; i <= i + 1'b1; end
4,5,6,7: // Send 4 nop clk for tDPL/tWR and tRP
begin rCMD <= _NOP; rDQM <= 2'b11; i <= i + 1'b1; end
/**********************************************/
8: // return i to 0
begin i <= 4'd0; end
/*********************************************/
endcase
这是我的程序。我从sdram读出来的图像如下图所示。频率大约才20mhz左右。但我的输入时钟s_clk有150Mhz。我想用猝发读让输出频率大些，怎么弄好
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发表于 2014-5-2 09:19:54
