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本帖最后由 zcy0517 于 2014-4-11 14:51 编辑
我做的是摄像头采集,sdram存储,vga输出。目前我使用摄像头的帧同步头来清零写入地址,用vga的帧同步头来清零读写入地址,且写偶数页时,读奇数页。我只对sdram输入0x001的数据(我把摄像头输出数据给改成单色的0x001,帧行同步保留),但读出来的数据有很多杂质,如0x088等。我怀疑读取到了很多没有赋值的区域。该怎么控制会解决这个问题?
(最后用这个程序初步调出来了稳定的0x001数据,放在这边大家共享,楼下还有一些列问题,望大家指教)
module fifo_Ctrl(addr,dpm,cs,
rst,clk150,valid2,key,
clk_cmos,vsync1,vsync2,clk100,
Raddr,Waddr);
///basic
output cs;
output[1:0] dpm;
assign cs=1'b1;
assign dpm=0;
///out
input rst;
input clk150;//in
input clk100;
input valid2;
input key; //key==0,wr;key==1,rd;
///in
input clk_cmos;
input vsync1;
input vsync2;
output[21:0] addr;
///try
output[21:0] Raddr;
output[21:0] Waddr;
reg flag;
reg[21:0] Raddr;
reg[21:0] Waddr;
reg[21:0] Endaddr;
reg[21:0] addr;
reg vsync1_buff1;
reg vsync1_buff2;
wire vsync1_req;
always @(posedge clk_cmos or negedge rst)
begin
vsync1_buff1<=vsync1;
vsync1_buff2<=vsync1_buff1;
end
assign vsync1_req = vsync1_buff1 & ~vsync1_buff2; //上升沿为1
reg vsync2_buff1;
reg vsync2_buff2;
wire vsync2_req;
always @(posedge clk100 or negedge rst)
begin
vsync2_buff1<=vsync2;
vsync2_buff2<=vsync2_buff1;
end
assign vsync2_req = vsync2_buff1 & ~vsync2_buff2; //上升沿为1
always @(posedge clk150 or negedge rst )
begin
if(!rst) begin flag<=0;Raddr<=0;Waddr<=0; end
else if(vsync1_req)
begin
{Endaddr[20:9],Endaddr[7:0]}<={Raddr[20:9],Raddr[7:0]};
{Raddr[20:9],Raddr[7:0]}<=0;
{Waddr[20:9],Waddr[7:0]}<=0;
if(flag==0) begin {Raddr[21],Raddr[8]}<=2'b10; {Waddr[21],Waddr[8]}<=2'b00; flag<=~flag; end
else if(flag==1) begin {Raddr[21],Raddr[8]}<=2'b00; {Waddr[21],Waddr[8]}<=2'b10;flag<=~flag; end
end
else if(key==1)//read
begin
if(Raddr[7:0]<8'hff) Raddr[7:0]<=Raddr[7:0]+1'b1;
else if(Raddr[7:0]==8'hff) begin
Raddr[7:0]<=0;
Raddr[20:9]<=Raddr[20:9]+1'b1;
end
end
else if({Waddr[20:9],Waddr[7:0]}=={Endaddr[20:9],Endaddr[7:0]}) //write
{Waddr[20:9],Waddr[7:0]}<=0;
else if(Waddr[7:0]<8'hff) Waddr[7:0]<=Waddr[7:0]+1'b1;
else if(Waddr[7:0]==8'hff) begin
Waddr[7:0]<=0;
Waddr[20:9]<=Waddr[20:9]+1'b1;
end
end
always @(posedge clk150 or negedge rst)
if(!rst) addr<=0;
else if(key==1) addr<=Raddr;
else if(key==0) addr<=Waddr;
endmodule
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阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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