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发表于 2013-11-14 12:57:49
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显示全部楼层
刚好在用的一个模块,你可以参考一下...
module msg_async
( // 5a d1 d2 d3 d4 a5
input wire clk_i,reset_i,
input wire [7:0] dat8_i,
output wire [15:0] kp_o,ki_o,k2_o,k3_o,
input wire dc_wr_i,dt_cr_i,
output wire dc_wc_o,dt_ry_o
);
reg [3:0] state;
reg dtry,dcwr;
reg [15:0] buf1,buf2,buf3,buf4;
reg [15:0] msg1,msg2,msg3,msg4;
assign dc_wc_o=dcwr;
assign dt_ry_o=dtry;
assign kp_o=msg1;
assign ki_o=msg2;
assign k2_o=msg3;
assign k3_o=msg4;
always @ (posedge clk_i or posedge reset_i)
begin
if (reset_i == 1'b1)
begin
state<=0;
dcwr<=0;
dtry<=0;
msg1<=0;
msg2<=0;
msg3<=0;
msg4<=0;
end
else
begin
if((dtry==1'b1)&&(dt_cr_i==1'b1)) dtry<=0;
if((dc_wr_i==1'b1)&&(dcwr==1'b0))
begin
dcwr<=1'b1;
case (state)
4'h0:
begin
if(dat8_i==8'h5a)
begin
state<=4'h1;
end
end
4'h1:
begin
buf1[15:8]<=dat8_i;
state<=4'h2;
end
4'h2:
begin
buf1[7:0]<=dat8_i;
state<=4'h3;
end
4'h3:
begin
buf2[15:8]<=dat8_i;
state<=4'h4;
end
4'h4:
begin
buf2[7:0]<=dat8_i;
state<=4'h5;
end
4'h5:
begin
buf3[15:8]<=dat8_i;
state<=4'h6;
end
4'h6:
begin
buf3[7:0]<=dat8_i;
state<=4'h7;
end
4'h7:
begin
buf4[15:8]<=dat8_i;
state<=4'h8;
end
4'h8:
begin
buf4[7:0]<=dat8_i;
state<=4'h0f;
end
4'h0f:
begin
if(dat8_i==8'ha5)
begin
dtry<=1;
msg1<=buf1;
msg2<=buf2;
msg3<=buf3;
msg4<=buf4;
end
state<=4'h0;
end
endcase
end
else
begin
dcwr<=dc_wr_i;
end
end
end
endmodule
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