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//prepare Enable
*sys_MISCCR |= (1<31); /*HS-SPI Select HSSPI_EN2 Must be set ‘1’*/
//Pin mux
*port_GPECON&=~(0x3f<<22);
*port_GPECON|=(1<<27)|(1<<25)|(1<<23); /*GPE13->SPICLK,GPE12->SPIMOSI,GPE11->SPIMISO; all clr*/
*port_GPLCON&=~(0x3<<26);
*port_GPLCON|=(1<<27);/*GPL13->SPISS,all clr*/
/*Pull/down-up disable*/
*port_GPEUDP&=~(0x3F<<22);
*port_GPLUDP&=~(0x3<<26);
//Clock on
*clk_SCLKCON|=(1<<14); /* For HS-SPI Enable HS-SPI_0 (EPLL) clock */
*clk_PCLKCON|=(1<<6); /* For HS-SPI Enable PCLK into the SPI_HS0 */
#if 1
//SPI Regs
/*1. Set Transfer Type. ( CPOL & CPHA set ) CPOL = 0, CPHA = 0 (Format A)*/
*spi_CH_CFG |= (1<<5); /*sw_rst enable*/
*spi_CH_CFG &= ~(1<<5); /*sw_rst disable*/
*spi_CH_CFG|=3<<2;
/*2. Set Clock configuration register. */
*spi_CLK_CFG=0x5; /*prescale=5*/
*spi_CLK_CFG|=(1<<8); /*Enable clock*/
/*3. Set HS_SPI MODE configuration register.*/
*spi_MODE_CFG|=(0x3FF<<19); /*Trailing count refresh*/
*spi_MODE_CFG|=(1<<5)|(1<<11); /*Triger level*/
/*4. Set HS_SPI INT_EN register. */
*spi_HS_SPI_INT_EN|=0x3F;
/*5. Set Packet Count configuration register if necessary. */
//*spi_SPI_PACKAGE_COUNTER_REG=0x105;
/*6. Set Tx or Rx Channel on. */
*spi_CH_CFG |= 1<<0; /*Tx channal on*/
*spi_CH_CFG |= 1<<1; /*Rx channal on*/
/*7. Set nSSout low to start Tx or Rx operation
A. Set nSSout Bit to low, then start TX data writing.
B. If auto chip selection bit is set, should not control nCS*/
*spi_SLAVE_SLECTION_REG|=(0xFF<<4);/*nCS_time_count*/
*spi_SLAVE_SLECTION_REG&=~(1<<0); /*Manual mode,Enable SPI_CS*/
/*8. test send Byte*/
*spi_SPI_TX_DATA = 0x55; |
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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