大家帮我看看cpld+sdram的代码问题(可下载整个工程包)

wwwjjj-1 · 发表于 2013-8-1 11:54:48

本帖最后由 wwwjjj-1 于 2013-8-1 14:28 编辑

问题
1、生成的地址有问题，仿真没问题；
2、在写的过程中，有漏写和飞溅。

wwwjjj-1 · 发表于 2013-8-1 11:55:55

代码如下：

sdram控制

//-----------------------------------------------------------------------------
module Sdram_Control
(
clk,rst_n,sd_init_ok,fifo_wruseDW,fifo_wr_reg,out_data,Sdram_data,
ramCK,ramDQM,ramBS,ramADR,ramCS,ramRAS,ramCAS,ramWE,ramDAT,
FillRow,FillCol,DispBS,FillBS,dat_in_resp,dat_in_act
);

input clk;
input rst_n;

input [2:0] fifo_wruseDW;
input [11:0]FillRow;
input [7:0]FillCol;
input [1:0]DispBS;
input [1:0]FillBS;
input [15:0]Sdram_data;
input dat_in_act;

output sd_init_ok;
output fifo_wr_reg;
output ramCK,ramCS,ramRAS,ramCAS,ramWE;
output [1:0]ramDQM,ramBS;
output [11:0]ramADR;
output [15:0] out_data;
inout [15:0] ramDAT;
output dat_in_resp;

//-----------------------------------------------------------------------------
reg sd_init_ok ; // System run enable
reg dat_in_resp;
reg [3:0] clk_cnt;
reg [2:0] loop_cnt; // Nop loop cnt
reg [11:0] DispRow;
reg [7:0] DispCol; // for 32Pages
reg [3:0]Refresh_cnt;
reg fifo_wr_reg;
//-----------------------------------------------------------------------------
reg refresh_en;
reg ramOE; // if "1",writer data to ram
reg ramRAS,ramCAS,ramWE;

reg [13:0] init_cnt;
reg [3:0] state_mode;
reg [3:0] next_state;

reg [11:0] ramADR;
reg [1:0] ramBS;
//-----------------------------------------------------------------------------
// wire [15:0] out_data;

//-----------------------------------------------------------------------------
assign ramCK = clk; // Ram Clock
assign ramDQM = 2'b00; // DQM is not used
assign ramCS = 1'b0;
assign ramDAT = ramOE ? Sdram_data: 16'hzzzz;
assign out_data = ramDAT;
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

always @(negedge clk or negedge rst_n)

if(!rst_n) begin
sd_init_ok <= 1'b0;
state_mode <= 4'd0;
ramADR <= 12'hfff;
ramRAS <= 1'b1;
ramCAS <= 1'b1;
ramWE <= 1'b1;
ramOE <= 1'b0;
init_cnt <= 14'h3fff;
Refresh_cnt <= 4'd0;
DispRow <= 12'd0;
DispCol <= 8'd0;
fifo_wr_reg <= 1'b0;
dat_in_resp <= 1'b0;
ramBS <= 2'b11;
loop_cnt <= 3'd0;
//rec_end <= 1'b0;
end
else if(sd_init_ok)begin

case(state_mode) //sdram read or writer or Auto-precharge
4'd0:
begin
ramRAS <= 1'b1;
ramCAS <= 1'b1;
ramWE <= 1'b1;
state_mode <= next_state;
end

4'd1:begin
// From init entry,Row Active
if(fifo_wruseDW<3'd4)
begin
ramRAS <= 1'b0;
ramCAS <= 1'b1;
ramWE <= 1'b1;
ramBS <= DispBS;
ramADR <= DispRow;
state_mode <= 4'd0;
next_state <= 4'd2;
end
else if(dat_in_act != dat_in_resp)begin
dat_in_resp <= !dat_in_resp;
state_mode <= 4'd5;
end
else state_mode <= 4'd1;
end

4'd2:
begin
ramRAS <= 1'b1;
ramCAS <= 1'b0;
ramWE <= 1'b1;
//loop_cnt <= 3'd1;
ramADR <= {4'b0100,DispCol};

if(DispRow[0] == 1'b0) begin

if(DispCol[7:2] == 6'h3f)begin
DispCol <= 8'd0;
DispRow <= DispRow + 1'b1;
end
else
DispCol[7:2] <= DispCol[7:2] + 1'b1;
end
else begin
if(DispCol == 8'd220) begin
DispCol <= 8'd0;
if(DispRow ==12'd543)
DispRow <= 12'd0;
else
DispRow <= DispRow + 1'b1;
refresh_en <= 1'b1;
end
else
DispCol[7:2] <= DispCol[7:2] + 1'b1;
end
state_mode <= 4'd0;//10;
next_state <= 4'd3; // Goto get data
end
4'd3:
begin
fifo_wr_reg <= 1'b1;
state_mode <= 4'd10;
loop_cnt <= 2; // 6 nop loops
next_state <= 4'd4; // Goto
end

4'd4:
begin
fifo_wr_reg <= 1'b0;
//loop_cnt <= 3;
state_mode <= 4'd0;//2
next_state <= 4'd8;
end

4'd5: // Bank Active for write
begin
ramRAS <= 0;
ramCAS <= 1;
ramWE <= 1;
ramOE <= 1;
ramBS <= FillBS;
ramADR <= FillRow;
state_mode <= 4'd0;
next_state <= 4'd6; // Goto write
end

4'd6: // Write with Auto-precharge
begin
ramRAS <= 1;
ramCAS <= 0;
ramWE <= 0;
ramADR <={4'b0100,FillCol};

state_mode <= 4'd7;
loop_cnt <= 3'd3; // 5 nop loops
next_state <= 4'd1; // Goto detect next state
end

4'd7: // Nop Loop cnt
begin
ramRAS <= 1;
ramCAS <= 1;
ramWE <= 1;

if(loop_cnt)
loop_cnt <= loop_cnt - 3'h1;
else begin
state_mode <= next_state;
ramOE <= 0;
end
end

4'd8:
begin
if(refresh_en)
begin
refresh_en <= 0;
state_mode <= 4'd9; // Next state is Auto Refresh
end
else
state_mode <= 4'd1; // Next state is read
end
4'd9: // Auto Refresh
begin
ramRAS <= 1'b0;
ramCAS <= 1'b0;
ramWE <= 1'b1;
loop_cnt <= 3'd2;
state_mode <= 4'd10;
next_state <= 4'd1; // Goto detect write or not
end

4'd10: // Nop for no write
begin
ramRAS <= 1;
ramCAS <= 1;
ramWE <= 1;
if(loop_cnt)
loop_cnt <= loop_cnt - 3'h1;
else
state_mode <= next_state;
end

endcase
end
else
begin
case(state_mode) //sdram init
4'd0: // Wait for 200us
begin
init_cnt <= init_cnt -1'b1;
ramRAS <= 1'b1;
ramCAS <= 1'b1;
ramWE <= 1'b1;
ramADR <= 12'hfff;
if(init_cnt == 14'd0)
state_mode <= 4'd2;

end

4'd1: // idle
begin
init_cnt <= init_cnt - 1'b1;
ramRAS <= 1'b1;
ramCAS <= 1'b1;
ramWE <= 1'b1;
ramBS <= 2'b11;
ramADR <= 12'hfff;
if(init_cnt == 14'd0)begin
if(Refresh_cnt> 4'd7) begin
state_mode <= 4'd4;
Refresh_cnt <= 4'd0;
end
else state_mode <= next_state;

end
end

4'd2: // Precharge All
begin
ramRAS <= 1'b0;
ramCAS <= 1'b1;
ramWE <= 1'b0;
//ramADR[10] <= 1'b1;//对所有行预充电
state_mode <= 4'd1;
next_state <= 4'd3;
init_cnt <= 14'd3;
end

4'd3: // Auto Refresh
begin
Refresh_cnt <= Refresh_cnt + 1'b1;
ramRAS <= 1'b0;
ramCAS <= 1'b0;
ramWE <= 1'b1;
init_cnt <= 14'd5;
state_mode <= 4'd1; // Goto idle
next_state <= 4'd3;
end
4'd4: // Mode Register Set
begin
ramRAS <= 1'b0;
ramCAS <= 1'b0;
ramWE <= 1'b0;
ramBS <= 2'b00;
ramADR <= 12'b0010_0010_0010; // CL=3,BL=4
state_mode <= 4'd1; // Goto idle
next_state <= 4'd5;
init_cnt <= 14'd8;
end
4'd5:
begin
ramRAS <= 1'b1;
ramCAS <= 1'b1;
ramWE <= 1'b1;
sd_init_ok <= 1'b1;
state_mode <= 4'd1;
end

endcase
end

endmodule

wwwjjj-1 · 发表于 2013-8-1 11:56:47

数据及地址产生

module Data_Generater
(

clk,rst_n,RI,rec_data,Sdram_data,
DispBS,FillBS,FillRow,FillCol,
dat_in_resp,dat_in_act
);

input clk;
input rst_n;
input RI;
input [7:0]rec_data;
input dat_in_resp;

output [15:0]Sdram_data;
output [1:0] DispBS;
output [1:0] FillBS;
output [11:0]FillRow;
output [7:0]FillCol;
output reg dat_in_act;

reg [7:0]Cmd_REG; //命令寄存器
reg [15:0] HLcolor;//前景色寄存器;
reg [15:0] BLcolor;//背景色寄存器
reg [8:0] begin_col;
reg [9:0] begin_row;
reg [8:0] end_col;
reg [9:0] end_row;
reg [1:0] dis_page;
reg [1:0] wr_page;
reg Cmd_flag;
reg [11:0] B_FillRow,E_FillRow;
reg [7:0]B_FillCol,E_FillCol;
reg[15:0]Sdram_data1,Sdram_data2;

assign DispBS = dis_page;
assign FillBS = wr_page;
assign FillRow = B_FillRow;
assign FillCol = B_FillCol;

assign Sdram_data = (R_FILL && !R_2D)? Sdram_data2 : Sdram_data1;

reg RI1,RI0;
always @(negedge clk or negedge rst_n)
if(!rst_n) begin
RI0 <= 1'b0;
RI1 <= 1'b0;
end
else begin
RI0 <= RI;
RI1 <= RI0;
end

wire pos_ri = ~RI1 && RI0;

reg rec_end;
reg [1:0]i,j;
reg R_2D,R_FILL;

always @(negedge clk or negedge rst_n)
if(!rst_n)
begin
Cmd_REG<=8'd0;
begin_col <= 9'd0;
begin_row <= 9'd0;
dis_page <= 2'b00;
wr_page <= 2'b00;
end_col <= 9'h1e0;
end_row <= 9'h110;
HLcolor <= 16'hffff;
BLcolor <= 16'h0000;
i<=2'd0;
Sdram_data1 <= 16'hffff;
Cmd_flag <= 1'b0;
R_2D <= 1'b0;
R_FILL<= 1'b0;
end
else if((pos_ri)&&(rec_data==8'hfe))Cmd_flag <= 1'b1;

else if((pos_ri) && (Cmd_flag)) begin Cmd_flag <= 1'b0;Cmd_REG <= rec_data;end

else
case(Cmd_REG)

8'h01: if(pos_ri)begin dis_page <= rec_data[1:0];end

8'h02: if(pos_ri)begin wr_page <= rec_data[1:0];end
8'h03:
case(i)
2'd0: if(pos_ri)begin BLcolor[15:8] <= rec_data; i <= 2'd1;end
2'd1: if(pos_ri)begin BLcolor [7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h04:
case(i)
2'd0: if(pos_ri)begin HLcolor[15:8] <= rec_data; i <= 2'd1;end
2'd1: if(pos_ri)begin HLcolor [7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h05:
case(i)
2'd0: if(pos_ri)begin begin_col[8] <= rec_data[0]; i <= 2'd1;end
2'd1: if(pos_ri)begin begin_col[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h06:
case(i)
2'd0: if(pos_ri)begin begin_row[9:8] <= rec_data[1:0]; i <= 2'd1;end
2'd1: if(pos_ri)begin begin_row[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h07:
case(i)
2'd0: if(pos_ri)begin end_col[8] <= rec_data[0]; i <= 2'd1;end
2'd1: if(pos_ri)begin end_col[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h08:
case(i)
2'd0: if(pos_ri)begin end_row[9:8] <= rec_data[1:0]; i <= 2'd1;end
2'd1: if(pos_ri)begin end_row[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h09:
case(i)
2'd0: begin Sdram_data1 <= HLcolor; i <= 2'd1;Cmd_REG<=8'd0;end
2'd1: begin i <= 2'd0;end
endcase
8'h0a:
case(i)
2'd0: begin Sdram_data1 <= BLcolor; i <= 2'd1;Cmd_REG<=8'd0;end
2'd1: begin i <= 2'd0;end
endcase
8'h0b:
case(i)
2'd0: begin R_2D <= 1'b1; i <= 2'd1;end
//2'd1:i <= 2'd2;
2'd1: begin i <= 2'd0;R_2D <= 1'b0;Cmd_REG<=8'd0;end
endcase
8'h0c:
case(i)
2'd0: begin R_FILL<= 1'b1; i <= 2'd1;end
2'd1:if(rec_end == 1'b1)begin i <= 2'd0;Cmd_REG<=8'd0;R_FILL<= 1'b0;end
endcase
default:begin
Cmd_REG<=8'd0;
end
endcase

reg [3:0]addr_cnt;
always @(negedge clk or negedge rst_n)
if(!rst_n)
begin
B_FillRow<=12'd0;
B_FillCol<=8'd0;
addr_cnt <= 4'd0;
rec_end <= 1'b0;
end
else
case(addr_cnt)
4'd0: if(R_2D || R_FILL) begin addr_cnt <= 4'd1;end
4'd1: begin
if(begin_col[8] ==1'b1)begin
B_FillRow <={2'b00,((begin_row << 1'b1)+1'b1)};
B_FillCol <= begin_col[7:0];
end
else begin
B_FillRow <={2'b00,(begin_row << 1'b1)};
B_FillCol <= begin_col[7:0];
end

if(end_col[8] ==1'b1)begin
E_FillRow <={2'b00,((end_row << 1'b1)+1'b1)};
E_FillCol <= end_col[7:0]-1'b1;
end
else begin
E_FillRow <={2'b00,(end_row << 1'b1)};
E_FillCol <= end_col[7:0]-1'b1;
end
addr_cnt <= 4'd2;
dat_in_act <= !dat_in_act;
end
4'd2: if(dat_in_act == dat_in_resp)begin
if(R_FILL)begin
case(j)
2'd0: if(pos_ri)begin
Sdram_data2[15:8] <= rec_data;
j<=2'd1;
end
2'd1: if(pos_ri)begin
Sdram_data2[7:0] <= rec_data;
j<=2'd2;
end
2'd2: begin
//dat_in_act <= !dat_in_act;
addr_cnt <= 4'd3;
j<=2'd0;
end
endcase
end
else begin
addr_cnt <= 4'd3;
//dat_in_act <= !dat_in_act;
end
end
4'd3: begin
addr_cnt <= 4'd4;
if(begin_col[8] == end_col[8]) begin
if(B_FillCol == E_FillCol)begin
B_FillCol <= begin_col[7:0];
if(B_FillRow == E_FillRow) begin
B_FillRow <=12'd0;
B_FillCol <= 8'd0;
rec_end <= 1'b1;
end
else
B_FillRow[11:1] <= B_FillRow[11:1]+ 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
else begin
if(B_FillRow[0] == 1'b1) begin
if(B_FillCol == E_FillCol)begin
B_FillCol <= begin_col[7:0];
if(B_FillRow == E_FillRow) begin
B_FillRow <= 12'd0;
B_FillCol <= 8'd0;
rec_end <= 1'b1;
end
else
B_FillRow <= B_FillRow + 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
else begin
if(B_FillCol == 8'hff)begin
B_FillCol <= 8'd0;
B_FillRow <= B_FillRow + 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
end
end
4'd4: begin
if(rec_end) begin addr_cnt <= 4'd0;rec_end <= 1'b0;end
else begin
dat_in_act <= !dat_in_act;
addr_cnt <= 4'd2;
//FillRow <= B_FillRow;
//FillCol <= B_FillCol;
end
end
default:begin addr_cnt <= 4'd0;end
endcase

endmodule

wwwjjj-1 · 发表于 2013-8-1 11:57:43

读fifo

module EASY_FIFO

(
aclr,
Wr_Clk,
nWr,
Din,
Rd_Clk,
nRd,
Dout,
wruserDW
);

input  aclr,Wr_Clk, nWr, Rd_Clk, nRd;

input  [15:0] Din;
output reg[15:0] Dout;
output  [2:0] wruserDW;

reg [15:0] Buff [15:0];
reg [2:0] Wr_Addr, Rd_Addr;

assign wruserDW = Wr_Addr-Rd_Addr;
always @ (posedge Rd_Clk)
begin
if (nRd )
Dout <= Buff[Rd_Addr];
else
Dout <= 16'd0;
end
always @ (posedge Wr_Clk)
begin
if (nWr )
Buff[Wr_Addr] <= Din;
else
Buff[Wr_Addr] <= Buff[Wr_Addr];
end
always @ (posedge Wr_Clk or negedge aclr)

if(!aclr) Wr_Addr<= 3'd0;
else if(nWr )Wr_Addr <= Wr_Addr + 1'b1;
else Wr_Addr<= Wr_Addr;

always @ (posedge Rd_Clk or negedge aclr)

if(!aclr) Rd_Addr <= 3'd0;
else if(nRd)Rd_Addr <= Rd_Addr + 1'b1;
else Rd_Addr <= Rd_Addr;

endmodule

wwwjjj-1 · 发表于 2013-8-1 11:58:36

tft时序

module TFT_CONTRL(

clk_in,
rst_n,
TFT_clk,
TFT_Hs,
TFT_Vs,
TFT_DE,
TFT_DISP,
wrfifo_en
//TFT_Addr
//x_cnt,y_cnt

);

input clk_in;    //66M
input rst_n;

output TFT_clk; //33M
output reg TFT_Hs;
output reg TFT_Vs;
output  TFT_DE;
output TFT_DISP;
output wrfifo_en;
//output [17:0]TFT_Addr;
reg [8:0] count_x;
reg [8:0] count_y;//count_x代表x列，count_y代表y行
reg [3:0] state_vs;
reg [3:0] state_hs;
reg clk,clk1;

parameter  value_areahs = 4'b0001,
h_front = 4'b0010,
h_sync  = 4'b0100,
h_back  = 4'b1000;
parameter  value_areavs = 4'b0001,
v_front = 4'b0010,
v_sync  = 4'b0100,
v_back  = 4'b1000;

parameter       hs_sync = 9'd1,
         hs_back = 9'd41,
      hs_area = 9'd479,
         hs_front = 9'd8;

parameter    vs_sync = 9'd9,
         vs_back = 9'd11,
         vs_area = 9'd271,
         vs_front = 9'd3;



assign TFT_DISP = 1'b1;
assign TFT_clk = ~clk;
assign wrfifo_en = ~clk1;
reg [2:0]cnt;
always @(posedge  clk_in or negedge rst_n)
if(!rst_n) begin
cnt<=3'd0;
end
else if(cnt==3'd5)begin
cnt<=3'd0;
end
else begin
cnt<=cnt +1'b1;
end
always @(posedge  clk_in or negedge rst_n)
if(!rst_n) begin
clk <= 1'b1;
end
else if(cnt>3'd2)begin
clk <= 1'b0;
end
else clk <= 1'b1;

always @(posedge  clk_in or negedge rst_n)
if(!rst_n) begin
clk1 <= 1'b1;
end
else if(cnt==3'd4)begin
clk1 <= 1'b0;
end
else clk1 <= 1'b1;

wire clk_en = (cnt==3'd2);

/************************行信号控制************************/

reg hs_areahs_flag;                //行扫描信号标志，低电平有效
reg Hs_carry;                      //行扫描进位标志位，用于场信号的计数器

always @(posedge  clk_in or negedge rst_n)
begin
if(!rst_n) begin
state_hs <= h_sync;
TFT_Hs <= 1'b0;
hs_areahs_flag <= 1'b1;
Hs_carry <= 1'b0;
count_x <= 9'd0;
end
else if(clk_en)begin
case(state_hs)
h_sync:
begin
count_x <= count_x + 1'b1;
Hs_carry <= 1'b0;          //仅有效一个时钟周期
if(count_x == hs_sync) begin
state_hs <= h_back;
TFT_Hs <= 1'b1;
count_x <= 9'd0;
end
else state_hs <= h_sync;
end
h_back:
begin
count_x <= count_x + 1'b1;
if(count_x == hs_back) begin
state_hs <= value_areahs;
hs_areahs_flag <= 1'b0; //有效场标志置0
count_x <= 9'd0;
end
else state_hs <= h_back;
end
value_areahs:
begin
count_x <= count_x + 1'b1;
if(count_x == hs_area) begin
state_hs <= h_front;
hs_areahs_flag <= 1'b1; //有效场标志置1
count_x <= 9'd0;
end
else state_hs <= value_areahs;
end
h_front:
begin

if(count_x == hs_front) begin
state_hs <= h_sync;
TFT_Hs <= 1'b0;
count_x <= 9'd0;
Hs_carry <= 1'b1;//仅有效一个时钟周期
count_x <= 9'd0;
end
else begin
count_x <= count_x + 1'b1;
state_hs <= h_front;
end
end
default:state_hs <= h_front;
endcase
end
end

/*************************场信号控制************************/
reg vs_areavs_flag;//场扫描信号标志，低电平有效
always @(posedge clk_in or negedge rst_n)
begin
if(!rst_n) begin
state_vs <= vs_sync;
vs_areavs_flag <= 1'b1;//有效场标志无效
count_y <= 9'd0;
TFT_Vs <= 1'b0;
end
else if((Hs_carry)&&(clk_en)) begin
case(state_vs)
v_sync:
begin
count_y <= count_y + 1'b1;
if(count_y == vs_sync) begin
state_vs <= v_back;
TFT_Vs <= 1'b1;
count_y <= 9'd0;
end
else state_vs <= v_sync;
end
v_back:
begin
count_y <= count_y + 1'b1;
if(count_y == vs_back) begin
vs_areavs_flag <= 1'b0;    //此时场扫描有效
state_vs <= value_areavs;
count_y <= 9'd0;
end
else state_vs <= v_back;
end
value_areavs:
begin
count_y <= count_y + 1'b1;
if(count_y == vs_area) begin
state_vs <= v_front;
vs_areavs_flag <= 1'b1;    //此时场扫描无效
count_y <= 9'd0;
end
else state_vs <= value_areavs;
end
v_front:
begin
if(count_y == vs_front) begin
state_vs <= v_sync;
count_y <= 9'd0;
TFT_Vs <= 1'b0;
end
else begin
count_y <= count_y + 1'b1;
state_vs <= v_front;
end
end
default:state_vs <= v_sync;
endcase
end
end

//assign TFT_Addr = (!hs_areahs_flag && !vs_areavs_flag )? {count_y,count_x}:18'd0;
assign TFT_DE = (!hs_areahs_flag && !vs_areavs_flag )? 1'b1:1'b0;
endmodule

wwwjjj-1 · 发表于 2013-8-1 11:59:31

还有就是串口模块

wwwjjj-1 · 发表于 2013-8-1 14:30:59

本帖最后由 wwwjjj-1 于 2013-8-2 09:31 编辑

经过修改Data_Generater

module Data_Generater
(

clk,rst_n,RI,rec_data,Sdram_data,
DispBS,FillBS,FillRow,FillCol,
dat_in_resp,dat_in_act
);

input clk;
input rst_n;
input RI;
input [7:0]rec_data;
input dat_in_resp;

output [15:0]Sdram_data;
output [1:0] DispBS;
output [1:0] FillBS;
output [11:0]FillRow;
output [7:0]FillCol;
output reg dat_in_act;

reg [7:0]Cmd_REG; //命令寄存器
reg [15:0] HLcolor;//前景色寄存器;
reg [15:0] BLcolor;//背景色寄存器
reg [8:0] begin_col;
reg [9:0] begin_row;
reg [8:0] end_col;
reg [9:0] end_row;
reg [1:0] dis_page;
reg [1:0] wr_page;
reg Cmd_flag;
reg [11:0] B_FillRow,E_FillRow;
reg [7:0]B_FillCol,E_FillCol;
reg[15:0]Sdram_data1,Sdram_data2;

assign DispBS = dis_page;
assign FillBS = wr_page;
assign FillRow = B_FillRow;
assign FillCol = B_FillCol;

assign Sdram_data = (R_FILL && !R_2D)? Sdram_data2 : Sdram_data1;

reg RI1,RI0;
always @(negedge clk or negedge rst_n)
if(!rst_n) begin
RI0 <= 1'b0;
RI1 <= 1'b0;
end
else begin
RI0 <= RI;
RI1 <= RI0;
end

wire pos_ri = ~RI1 && RI0;

reg rec_end;
reg [1:0]i,j;
reg R_2D,R_FILL;

always @(negedge clk or negedge rst_n)
if(!rst_n)
begin
Cmd_REG<=8'd0;
begin_col <= 9'd0;
begin_row <= 9'd0;
dis_page <= 2'b00;
wr_page <= 2'b00;
end_col <= 9'h1e0;
end_row <= 9'h110;
HLcolor <= 16'hffff;
BLcolor <= 16'h0000;
i<=2'd0;
Sdram_data1 <= 16'hffff;
Cmd_flag <= 1'b0;
R_2D <= 1'b0;
R_FILL<= 1'b0;
end
else if((pos_ri)&&(rec_data==8'hfe))Cmd_flag <= 1'b1;

else if((pos_ri) && (Cmd_flag)) begin Cmd_flag <= 1'b0;Cmd_REG <= rec_data;end

else
case(Cmd_REG)

8'h01: if(pos_ri)begin dis_page <= rec_data[1:0];end

8'h02: if(pos_ri)begin wr_page <= rec_data[1:0];end
8'h03:
case(i)
2'd0: if(pos_ri)begin BLcolor[15:8] <= rec_data; i <= 2'd1;end
2'd1: if(pos_ri)begin BLcolor [7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h04:
case(i)
2'd0: if(pos_ri)begin HLcolor[15:8] <= rec_data; i <= 2'd1;end
2'd1: if(pos_ri)begin HLcolor [7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h05:
case(i)
2'd0: if(pos_ri)begin begin_col[8] <= rec_data[0]; i <= 2'd1;end
2'd1: if(pos_ri)begin begin_col[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h06:
case(i)
2'd0: if(pos_ri)begin begin_row[9:8] <= rec_data[1:0]; i <= 2'd1;end
2'd1: if(pos_ri)begin begin_row[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h07:
case(i)
2'd0: if(pos_ri)begin end_col[8] <= rec_data[0]; i <= 2'd1;end
2'd1: if(pos_ri)begin end_col[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h08:
case(i)
2'd0: if(pos_ri)begin end_row[9:8] <= rec_data[1:0]; i <= 2'd1;end
2'd1: if(pos_ri)begin end_row[7:0]<= rec_data; i <= 2'd2;end
2'd2: begin i <= 2'd0;end
endcase
8'h09:
case(i)
2'd0: begin Sdram_data1 <= HLcolor; i <= 2'd1;Cmd_REG<=8'd0;end
2'd1: begin i <= 2'd0;end
endcase
8'h0a:
case(i)
2'd0: begin Sdram_data1 <= BLcolor; i <= 2'd1;Cmd_REG<=8'd0;end
2'd1: begin i <= 2'd0;end
endcase
8'h0b:
case(i)
2'd0: begin R_2D <= 1'b1; i <= 2'd1;end
//2'd1:i <= 2'd2;
2'd1: begin i <= 2'd0;R_2D <= 1'b0;Cmd_REG<=8'd0;end
endcase
8'h0c:
case(i)
2'd0: begin R_FILL<= 1'b1; i <= 2'd1;end
2'd1:if(rec_end == 1'b1)begin i <= 2'd0;Cmd_REG<=8'd0;R_FILL<= 1'b0;end
endcase
default:begin
Cmd_REG<=8'd0;
end
endcase

reg [3:0]addr_cnt;
always @(negedge clk or negedge rst_n)
if(!rst_n)
begin
B_FillRow<=12'd0;
B_FillCol<=8'd0;
addr_cnt <= 4'd0;
rec_end <= 1'b0;
end
else
case(addr_cnt)
4'd0: if(R_2D || R_FILL) begin addr_cnt <= 4'd1;end
4'd1: begin
if(begin_col[8] ==1'b1)begin
B_FillRow <={2'b00,((begin_row << 1'b1)+1'b1)};
B_FillCol <= begin_col[7:0];
end
else begin
B_FillRow <={2'b00,(begin_row << 1'b1)};
B_FillCol <= begin_col[7:0];
end
addr_cnt <= 4'd2;
end
4'd2:begin
if(end_col[8] ==1'b1)begin
E_FillRow <={2'b00,((end_row << 1'b1)+1'b1)};
E_FillCol <= end_col[7:0]-1'b1;
end
else begin
E_FillRow <={2'b00,(end_row << 1'b1)};
E_FillCol <= end_col[7:0]-1'b1;
end
addr_cnt <= 4'd3;
dat_in_act <= !dat_in_act;//在此没有数据接收，就开始写了！！！！ end
4'd3: if(dat_in_act == dat_in_resp)begin
if(R_FILL)begin
case(j)
2'd0: if(pos_ri)begin
Sdram_data2[15:8] <= rec_data;
j<=2'd1;
end
2'd1: if(pos_ri)begin
Sdram_data2[7:0] <= rec_data;
j<=2'd2;
end
2'd2: begin
//dat_in_act <= !dat_in_act;
addr_cnt <= 4'd4;
j<=2'd0;
end
endcase
end
else begin
addr_cnt <= 4'd4;
//dat_in_act <= !dat_in_act;
end
end
4'd4: begin
addr_cnt <= 4'd5;
if(begin_col[8] == end_col[8]) begin
if(B_FillCol == E_FillCol+1'b1)begin
B_FillCol <= begin_col[7:0];
if(B_FillRow == E_FillRow) begin
B_FillRow <=12'd0;
B_FillCol <= 8'd0;
rec_end <= 1'b1;
end
else
B_FillRow[11:1] <= B_FillRow[11:1]+ 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
else begin
if(B_FillRow[0] == 1'b1) begin
if(B_FillCol == E_FillCol+1'b1)begin
B_FillCol <= begin_col[7:0];
if(B_FillRow == E_FillRow) begin
B_FillRow <= 12'd0;
B_FillCol <= 8'd0;
rec_end <= 1'b1;
end
else
B_FillRow <= B_FillRow + 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
else begin
if(B_FillCol == 8'hff)begin
B_FillCol <= 8'd0;
B_FillRow <= B_FillRow + 1'b1;
end
else
B_FillCol <= B_FillCol + 1'b1;
end
end
end
4'd5: begin
if(rec_end) begin addr_cnt <= 4'd0;rec_end <= 1'b0;end
else begin
dat_in_act <= !dat_in_act;
addr_cnt <= 4'd3;
//FillRow <= B_FillRow;
//FillCol <= B_FillCol;
end
end
default:begin addr_cnt <= 4'd0;end
endcase

endmodule

wwwjjj-1 · 发表于 2013-8-1 14:38:09

屏有部分损坏，手机拍的效果不太好。

红快下边的白黑条，最左边的黑线应在最右边

wwwjjj-1 · 发表于 2013-8-1 14:48:17

工程文件

KSCNN · 发表于 2013-8-1 21:18:13

好的，学习一下

pontiff · 发表于 2013-8-1 23:45:55

我现在一看别人写的或者自己N年以前写的茫茫多的代码就头大

wwwjjj-1 · 发表于 2013-8-2 08:18:20

经过修改，现在生成的坐标已没有问题，只是还有漏写和飞溅现象。

u123321 · 发表于 2013-8-2 08:50:01

下载看看，谢谢分享

huchl · 发表于 2013-10-9 12:58:53

是不是和单片机共地有问题，这几天我也遇到了漏写现象。多共几根地试试

cdlxzlp · 发表于 2013-10-12 11:19:50

楼主还有没有空板子和电路图啊搞来也研究研究啊

youpeng · 发表于 2013-10-16 13:20:52

再次支持！
sdram是什么型号？

大家帮我看看cpld+sdram的代码问题(可下载整个工程包)

阿莫论坛20周年了！感谢大家的支持与爱护！！

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