vhdl语法没搞懂。帖子中报n个语法错误。请高手帮忙

zhongpeng123

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity Delay1 is
port(
       CLK,SYNC:in bit;
       Delay:out bit
       );
end;

architecture DELAY of Delay1 is

signal dlyen: std_logic;

Process(CLK,SYNC)
  Variable cnt1,cnt2,cnt3,dly_en1,dly_en  : integer:=0;
begin  
  dlyen<=SYNC or dly_en;
  if(dlyen='0') then
    Delay<='0';
    elsif CLK'event and CLK='1' then
      if cnt3<30 then
          dly_en<='1';cnt3:=cnt3+1;
      else
          dly_en<='0';cnt3:=0;
      end if;
      if cnt1>=20 then
        dly_en1:=1;
      else cnt1:=cnt1+1;
      end if;
      if dly_en1=1 then
        if cnt2>=10 then
        dly_en1:=0; cnt1:=0;cnt2:=0;
      else cnt2:=cnt2+1;
     end if;
  end if;
end if;
end process;
end;

gagmeng

把错误贴上来

zhongpeng123

Error (10500): VHDL syntax error at DELAY1.vhd(16) near text "Process";  expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at DELAY1.vhd(22) near text "if";  expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at DELAY1.vhd(22) near text "then";  expecting "<="
Error (10500): VHDL syntax error at DELAY1.vhd(24) near text "elsif";  expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at DELAY1.vhd(24) near text "and";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at DELAY1.vhd(26) near text ":=";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at DELAY1.vhd(28) near text ":=";  expecting "(", or "'", or "."
Error: Quartus II Create Symbol File was unsuccessful. 7 errors, 0 warnings
        Info: Allocated 184 megabytes of memory during processing
        Error: Processing ended: Fri Jul 12 15:57:16 2013
        Error: Elapsed time: 00:00:02

zhongpeng123

gagmeng 发表于 2013-7-12 16:12
把错误贴上来

新手，谢谢指导。

avrwoo

第一个错误，结构体的BEGIN丢了。另外整形的变量通常要限定范围，如INTEGER RANGE 0 TO 10;

40130064

语法基本正确，少个begin ，数据类型没完全搞清。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity Delay1 is
port(
       CLK,SYNC:in std_logic;
       Delay:out std_logic
       );
end;
architecture DELAY of Delay1 is
signal dlyen,dly_en: std_logic;
begin  
Process(CLK,SYNC)
Variable cnt1,cnt2,cnt3,dly_en1: integer:=0;
begin  
  if((dly_en='0')and(dlyen='0')) then
    Delay<='0';
    elsif CLK'event and CLK='1' then
      if cnt3<30 then
          dly_en<='1';cnt3:=cnt3+1;
      else
          dly_en<='0';cnt3:=0;
      end if;
      if cnt1>=20 then
        dly_en1:=1;
      else cnt1:=cnt1+1;
      end if;
      if dly_en1=1 then
        if cnt2>=10 then
        dly_en1:=0; cnt1:=0;cnt2:=0;
      else cnt2:=cnt2+1;
     end if;
  end if;
end if;
end process;
end;

zhongpeng123

呵呵，水平太差，没爬就开始跑了。最近再看看书，学习学习

zhongpeng123

40130064 发表于 2013-7-13 11:51
语法基本正确，少个begin ，数据类型没完全搞清。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

没有了sync，逻辑好像有问题吧

40130064

if((dly_en='0')and(sync='0')) then
还是换个语言吧，用这个的人相对少了。虽然我个人还是觉得VHDL好点。

zhongpeng123

公司的规定，没办法。硬件电路设计，临时安排干干这个