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![](static/image/common/ico_lz.png)
楼主 |
发表于 2013-7-11 10:38:40
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这是我写的fifo,大家看看,应如何修改??
module EASY_FIFO
(
aclr,
Wr_Clk,
nWr,
Din,
Rd_Clk,
nRd,
Dout,
wruser
);
input aclr,Wr_Clk, nWr, Rd_Clk, nRd;
input [15:0] Din;
output [15:0] Dout;
output [3:0] wruser;
reg [15:0] Buff [7:0];
reg [3:0] Wr_Addr, Rd_Addr;
assign Dout = Buff[Rd_Addr];
assign wruser = Wr_Addr-Rd_Addr;//?????这里有问题
always @ (posedge Wr_Clk)
begin
if (~nWr )
Buff[Wr_Addr] <= Din;
else
Buff[Wr_Addr] <= Buff[Wr_Addr];
end
always @ (posedge Wr_Clk or negedge aclr)
if(!aclr) Wr_Addr<= 4'd0;
else if(~nWr)Wr_Addr <= Wr_Addr + 1'b1
else Wr_Addr<= Wr_Addr;
always @ (posedge Rd_Clk or negedge aclr)
if(!aclr) Rd_Addr <= 4'd0;
else if(~nRd)Rd_Addr <= Rd_Addr + 1'b1
else Rd_Addr <= Rd_Addr;
endmodule
主要想法是,简单可用!! |
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