|
发表于 2013-6-1 23:23:55
|
显示全部楼层
如果对转换时间要求不高,可以用计数的方法,这样占用的资源非常少,如下:
module Hex2Dec(
//Clocks
iClk_40, //Clock
iReset_N, //Reset
//Hex intput
iHex, //Hex input
//Decimal output
oDigit0, //Digit 0
oDigit1 //Digit 1
);
/* PORT declarations
*/
//Clocks input
input iClk_40; //Clock
input iReset_N; //Reset
//Hex intput
input [ 7: 0] iHex; //Hex input
//Decimal output
output reg [ 3: 0] oDigit0; //Digit 0
output reg [ 3: 0] oDigit1; //Digit 1
/* REG/WIRE declarations
*/
reg [ 7: 0] hexCnt; //Hex counter
reg [ 7: 0] decCnt; //Decimal counter
wire endOfCnt; //End of counting
/* LOGIC Descriptions
*/
//Decimal output
always @(posedge iClk_40)
if(endOfCnt) begin
oDigit0 <= decCnt[ 3: 0];
oDigit1 <= decCnt[ 7: 4];
end
//Hex down-counting
always @(posedge iClk_40 or negedge iReset_N)
if(!iReset_N) begin
hexCnt <= 8'h00;
end
else if(endOfCnt) begin
hexCnt <= iHex;
end
else begin
hexCnt <= hexCnt - 8'h01;
end
//End of counting
assign endOfCnt = (hexCnt == 8'h00);
//Decimal up-counting
always @(posedge iClk_40 or negedge iReset_N)
if(!iReset_N) begin
decCnt <= 8'd0;
end
else if(endOfCnt) begin
decCnt <= 8'd0;
end
else begin
//Digit 0
if(decCnt[3: 0] == 4'd9) decCnt[3: 0] <= 4'd0;
else decCnt[3: 0] <= decCnt[3: 0] + 4'd1;
//Digit 1
if(decCnt[3: 0] == 4'd9) decCnt[7: 4] <= decCnt[7: 4] + 4'd1;
end
endmodule //Hex2Dec |
|