用TERASIC_VGA做的UCGUI有問題

lgeorge123 · 发表于 2013-6-1 18:24:21

本帖最后由 lgeorge123 于 2013-6-1 18:31 编辑

在網上下了一个DE1_NIOS 用TERASIC_VGA 的程序 , 打算移植UCGUI , 編譯到 , HS 和 VS 有訊號 , 出 GUI_BLUE 可是紅色 , 藍色和綠色有奇怪訊號 , 各位可否代我看看有何不对!!
用的是QUARTUS 12.1 和 ECLIPSE .....
文件太大 , 只好逐个列出

module DE1_NIOS(
CLOCK_50, // 50 MHz
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE, // SDRAM Write Enable
DRAM_CAS, // SDRAM Column Address Strobe
DRAM_RAS, // SDRAM Row Address Strobe
DRAM_CS, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB, // SRAM High-byte Data Mask
SRAM_LB, // SRAM Low-byte Data Mask
SRAM_WE, // SRAM Write Enable
SRAM_CE, // SRAM Chip Enable
SRAM_OE, // SRAM Output Enable
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red[3:0]
VGA_G, // VGA Green[3:0]
VGA_B, // VGA Blue[3:0]
);
input CLOCK_50; // 50 MHz
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE; // SDRAM Write Enable
output DRAM_CAS; // SDRAM Column Address Strobe
output DRAM_RAS; // SDRAM Row Address Strobe
output DRAM_CS; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB; // SRAM High-byte Data Mask
output SRAM_LB; // SRAM Low-byte Data Mask
output SRAM_WE; // SRAM Write Enable
output SRAM_CE; // SRAM Chip Enable
output SRAM_OE; // SRAM Output Enable
//////////////////////// VGA ////////////////////////////
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output [3:0] VGA_R; // VGA Red[3:0]
output [3:0] VGA_G; // VGA Green[3:0]
output [3:0] VGA_B; // VGA Blue[3:0]
wire system_reset_n;
assign system_reset_n = 1'b1;
//sys_pll sys_pll_inst(
// .areset(1'b0),
// .inclk0(CLOCK_24),
// .c0(),
// .locked()
// );
DE1_SOPC DE1_SOPC_Inst(
// 1) global signals:
.clk_50(CLOCK_50),
.pll_pclk(),
.pll_sdram(DRAM_CLK),
.reset_n(system_reset_n),
// the_sdram
.zs_addr_from_the_sdram(DRAM_ADDR),
.zs_ba_from_the_sdram({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram(DRAM_CAS),
.zs_cke_from_the_sdram(DRAM_CKE),
.zs_cs_n_from_the_sdram(DRAM_CS),
.zs_dq_to_and_from_the_sdram(DRAM_DQ),
.zs_dqm_from_the_sdram({DRAM_UDQM, DRAM_LDQM}),
.zs_ras_n_from_the_sdram(DRAM_RAS),
.zs_we_n_from_the_sdram(DRAM_WE),
// the_sram
.SRAM_ADDR_from_the_sram(SRAM_ADDR),
.SRAM_CE_N_from_the_sram(SRAM_C),
.SRAM_DQ_to_and_from_the_sram(SRAM_DQ),
.SRAM_LB_N_from_the_sram(SRAM_LB),
.SRAM_OE_N_from_the_sram(SRAM_OE),
.SRAM_UB_N_from_the_sram(SRAM_UB),
.SRAM_WE_N_from_the_sram(SRAM_WE),
// the_vga
.vga_b_from_the_vga(video_b8),
.vga_clk_from_the_vga(),
.vga_de_from_the_vga(),
.vga_g_from_the_vga(video_g8),
.vga_hs_from_the_vga(VGA_HS),
.vga_r_from_the_vga(video_r8),
.vga_vs_from_the_vga(VGA_VS)
);
wire [7:0] video_r8;
wire [7:0] video_g8;
wire [7:0] video_b8;
assign VGA_R = video_r8[7:4];
assign VGA_G = video_g8[7:4];
assign VGA_B = video_b8[7:4];
endmodule
[code]/*
*********************************************************************************************************
* uC/GUI V3.98
* Universal graphic software for embedded applications
*
*
* 湣/GUI is protected by international copyright laws. Knowledge of the
* source code may not be used to write a similar product. This file may
* only be used in accordance with a license and should not be redistributed
* in any way. We appreciate your understanding and fairness.
*
----------------------------------------------------------------------
File : LCDConf_1375_C8_C320x240.h
Purpose : Sample configuration file
----------------------------------------------------------------------
*/
#ifndef LCDCONF_H
#define LCDCONF_H
#include"io.h"
#include"system.h"
/*********************************************************************
*
* General configuration of LCD
*
**********************************************************************
*/
#define LCD_XSIZE (240) /* X-resolution of LCD, Logical coor. */
#define LCD_YSIZE (320) /* Y-resolution of LCD, Logical coor. */
#define LCD_BITSPERPIXEL (16)
#define LCD_FIXEDPALETTE (565)
#define LCD_SWAP_RB (1)
#define LCD_CONTROLLER 3200
#define SRAM 0x01880000
/*********************************************************************
*
* Full bus configuration
*
**********************************************************************
*/
#define LCD_READ_MEM(Off) IORD_32DIRECT((U32)SRAM_BASE,(U32)(Off))
#define LCD_WRITE_MEM(Off,data) IOWR_32DIRECT((U32)SRAM_BASE,(U32)(Off),data)
#define LCD_READ_REG(Off) *((volatile U16*)(0xc1ffe0+(((U16)(Off))<<1)))
#define LCD_WRITE_REG(Off,data) *((volatile U16*)(0xc1ffe0+(((U16)(Off))<<1)))=data
#define LCD_INIT_CONTROLLER() LCD_Controller_Init()
/*********************************************************************
*
* Define contents of registers
*
**********************************************************************
*/
#define LCD_REG0 (0) /* Product code */
#define LCD_REG1 (0x23) /* Mode reg 0. 0 for 4 bit mono LCD */ \
/* 1 for 8 bit mono LCD */ \
/* 0x23 for 8 bit color LCD */ \
|(1<<2) /* Mask FPSHIFT during h.non-display */
#define LCD_REG2 ((3<<6) /* Mode reg 1: Bits per pixel 0:1, 1:2, 2:4, 3:8 */ \
|(1<<5) /* High performance bit for accel. of CPU access */ \
|(1<<4) /* Input clock divide */ \
|(0<<3) /* Display blank */ \
|(0<<2) /* Frame repeat */ \
|(0<<1) /* HW video invert enable */ \
|(0<<0)) /* SW video invert */
#define LCD_REG3 /* Mode reg 2. 0 for 4 bit mono LCD */ \
(0<<7) /* LUT bypass */ \
|(0<<3) /* LCDPWR override */ \
|(0<<2) /* hw power save enable */ \
|(3<<0) /* Software power save :3 = normal operation */
#define LCD_REG4 (LCD_XSIZE/8-1) /* horizontal panel size*/
#define LCD_REG5 ((LCD_YSIZE-1)&255) /* Vert. panel size, lsb */
#define LCD_REG6 ((LCD_YSIZE-1)>>8) /* Vert. panel size, msb */
#define LCD_REG7 (0) /* FPLine start position (TFT only) */
#define LCD_REG8 (31) /* H.non display period (0 usually O.K.)*/
#define LCD_REG9 (0) /* FPFrame start pos. (TFT only) */
#define LCD_REGA (0) /* v.non display period */
#define LCD_REGB (0) /* mod rate register 0: every frame */
#define LCD_REGC (0) /* Screen 1 start lsb */
#define LCD_REGD (0) /* Screen 1 start msb */
#define LCD_REG12 (LCD_BITSPERPIXEL*(LCD_VXSIZE-LCD_XSIZE)/16) /* Memory Address offset (usually 0) */
#define LCD_REG13 LCD_REG5 /* Vert. screen 1 size, lsb */
#define LCD_REG14 LCD_REG6 /* Vert. screen 1 size, msb */
#define LCD_REG1B (0) /* No swivel mode (use 0xc0 for alt.swivel) */
#define LCD_REG1C (0x78) /* bytes per line (stride, for swivel mode only) */
/*********************************************************************
*
* Init sequence for 16 bit access
*
**********************************************************************
*/
#if !LCD_SWAP_BYTE_ORDER
#define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d0)<<8) | (d1))
#else
#define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d1)<<8) | (d0))
#endif
#endif /* LCDCONF_H */

复制代码

用TERASIC_VGA做的UCGUI有問題

本帖子中包含更多资源

阿莫论坛20周年了！感谢大家的支持与爱护！！