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用FPGA驱动OV7670，采集图像显示到TFT上。下面的代码是OV7670采集模块，我想问下这个能直接接到TFT上显示吗？OV7670和TFT的初始化都已经弄好了
module cmos_top(
iRST_N,
clk,
//ov7670
ov7670_xclk,
ov7670_pclk,
ov7670_data_8bit,
iVSYNC,//vsync
iHSYNC,//hsync
lcd2_cs,
lcd2_wr,
lcd2_rs,
lcd2_reset,
lcd2_rd,
lcd2_data16,
oDVAL,
lcd_data_valid
);
input iRST_N;
input clk;
//ov7670
output ov7670_xclk;
input ov7670_pclk;
input [7:0] ov7670_data_8bit;
input iVSYNC;
input iHSYNC;
//tft
output lcd2_cs;
output lcd2_wr;
output lcd2_rs;
output lcd2_reset;
output lcd2_rd;
output [15:0] lcd2_data16;
/////////////////////////////////
//Output Sensor Data
output oDVAL;
output lcd_data_valid;
assign ov7670_xclk = clk;
assign SCLK = ov7670_pclk;
assign lcd2_wr = reg_lcd2_wr;
assign lcd2_rs = 1'b1;
assign lcd2_rd = 1'b1;
assign lcd2_cs = 1'b0;
assign lcd2_reset = 1'b1;
assign lcd2_data16[15:0] = ov7670_data_16bit[15:0];
reg Pre_FVAL;
reg mCCD_FVAL;
reg mCCD_LVAL;
reg [10:0] X_Cont;
reg [10:0] Y_Cont;
assign i0v7670_data_8bit[7:0] = ov7670_data_8bit[7:0];
//assign oDVAL = mCCD_FVAL&mCCD_LVAL;
assign oDVAL = ~iVSYNC;// tft_outenable & (~iVSYNC);
wire [7:0] i0v7670_data_8bit;
////////////////////////////////
////Sensor data capture
assign iFVAL = iVSYNC;
reg [1:0] temp_count;
always@(posedge SCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
Pre_FVAL <= 0;
mCCD_FVAL <= 0;
mCCD_LVAL <= 0;
X_Cont <= 0;
Y_Cont <= 0;
end
else
begin
Pre_FVAL <= iFVAL;
if( {Pre_FVAL,iFVAL}==2'b10)
mCCD_FVAL <= 1;
else if({Pre_FVAL,iFVAL}==2'b01)
mCCD_FVAL <= 0;
mCCD_LVAL <= iHSYNC;
if(mCCD_FVAL)
begin
if(mCCD_LVAL)
begin
X_Cont <= X_Cont+1;
if(X_Cont==639)
begin
X_Cont <= 0;
Y_Cont <= Y_Cont+1;
end
end
end
else
begin
X_Cont <= 0;
if(temp_count == 3)
begin
Y_Cont <= 0;
temp_count <= 2'b00;
end
else
temp_count <= temp_count + 1'b1;
end
end
end
///////////////////////////////////////////////////////
//ov7660 data 8 bit to 16 bit
//功 能：将输入的8位数据转换成16位，同时进行位转换。
//转换后的数据符合TFT 数据输入格式
reg data_change_state;
reg [7:0] pre_i0v7670_data_8bit;
reg [15:0] ov7670_data_16bit;
always@(posedge SCLK or negedge iRST_N)
if(!iRST_N)
begin
data_change_state <= 1'b0;
ov7670_data_16bit<=16'd0;
end
else
begin
if(iHSYNC & mCCD_FVAL)
case(data_change_state)
1'b0 : begin
pre_i0v7670_data_8bit[7:0] <= i0v7670_data_8bit[7:0];
data_change_state <= 1'b1;
end
1'b1 : begin
ov7670_data_16bit[15:0] <= {pre_i0v7670_data_8bit[7:0],i0v7670_data_8bit[7:0]};
data_change_state <= 1'b0;
end
default : data_change_state <= 1'b0;
endcase
end
//SYNC CCD ouput CLK and pixel DATA
reg reg_lcd2_wr;
reg write_state;
reg lcd_data_valid;
always@(negedge SCLK or negedge iRST_N)
if(!iRST_N)
begin
reg_lcd2_wr <= 1'b1;
write_state <= 1'b0;
lcd_data_valid <= 1'b0;
end
else
case(write_state)
0 : if(iHSYNC&(Y_Cont == 0)&dava_valid)
begin
reg_lcd2_wr <= ~reg_lcd2_wr;
write_state <= 1'b1;
lcd_data_valid <= 1'b1;
end
else
begin
reg_lcd2_wr <= 1'b1;
lcd_data_valid <= 1'b0;
end
1 : begin
if(iHSYNC)//ilval
reg_lcd2_wr <= ~reg_lcd2_wr;
else
reg_lcd2_wr <= 1'b1;
if(Y_Cont < 240)
write_state <= 1'b1;
else
begin
write_state <= 1'b0;
lcd_data_valid <= 1'b0;
end
end
endcase
//Wait for Sensor output Data valid
reg [2:0] Frame_Cont;
reg dava_valid;//dava valid
always@(posedge SCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
Frame_Cont <= 0;
dava_valid<=0;
end
else
begin
if({Pre_FVAL,iFVAL}==2'b10)
if(Frame_Cont < 7)//5/7
begin
Frame_Cont <= Frame_Cont+1;
dava_valid <= 1'b0;
end
else
dava_valid <= 1'b1;
end
end
endmodule
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阿莫论坛20周年了！感谢大家的支持与爱护！！
曾经有一段真挚的爱情摆在我的面前，我没有珍惜，现在想起来，还好我没有珍惜……
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发表于 2013-4-30 10:29:13
