|
最近在做fpga的vga的显示,把一张图像转化为.coe文件储存rom,通过vga接口显示图像,总是显示不了,希望大神能够解答。附上程序
`timescale 1ns / 1ps
module vgab(clk, rst, hsync, vsync, vga_r, vga_g, vga_b);
input clk;
input rst;
output hsync;
output vsync;
output [2:0] vga_r;
output [2:0] vga_g;
output [1:0] vga_b;
wire pclk;
wire valid;
wire [9:0] h_cnt;
wire [9:0] v_cnt;
reg [7:0] vga_data;
reg [17:0] rom_addr;
wire [7:0] douta;
reg [1:0] rClk;
always@(posedge clk) rClk<= rClk+1;//rclk为25MHz
assign plck= rClk[0];
logo_rom u1 (
.clka(pclk), // input clka
.addra(rom_addr), // input [12 : 0] addra
.douta(douta) // output [7 : 0] douta
);
vga_640x480 u2 (
.pclk(pclk),
.reset(rst),
.hsync(hsync),
.vsync(vsync),
.valid(valid),
.h_cnt(h_cnt),
.v_cnt(v_cnt)
);
always @(posedge pclk or negedge rst)
begin
if (!rst)
vga_data <= 8'b00000000;
else
begin
if (valid == 1'b0)
begin
vga_data <= 8'b00000000;
rom_addr <= 18'b000000000000000010;
end
else
begin
rom_addr <= rom_addr + 18'b000000000000000001;
vga_data <= douta;
end
end
end
assign vga_r = vga_data[7:5];
assign vga_g = vga_data[4:2];
assign vga_b = vga_data[1:0];
endmodule
`timescale 1 ns / 1 ns
module vga_640x480(pclk, reset, hsync, vsync, valid, h_cnt, v_cnt);
input pclk;
input reset;
output hsync;
output vsync;
output valid;
output [9:0] h_cnt;
output [9:0] v_cnt;
parameter h_frontporch = 96;
parameter h_active = 144;
parameter h_backporch = 784;
parameter h_total = 800;
parameter v_frontporch = 2;
parameter v_active = 35;
parameter v_backporch = 515;
parameter v_total = 525;
reg [9:0] x_cnt;
reg [9:0] y_cnt;
wire h_valid;
wire v_valid;
always @(posedge reset or posedge pclk)
if (reset == 1'b1)
x_cnt <= 1;
else
begin
if (x_cnt == h_total)
x_cnt <= 1;
else
x_cnt <= x_cnt + 1;
end
always @(posedge pclk)
if (reset == 1'b1)
y_cnt <= 1;
else
begin
if (y_cnt == v_total & x_cnt == h_total)
y_cnt <= 1;
else if (x_cnt == h_total)
y_cnt <= y_cnt + 1;
end
assign hsync = ((x_cnt > h_frontporch)) ? 1'b1 :
1'b0;
assign vsync = ((y_cnt > v_frontporch)) ? 1'b1 :
1'b0;
assign h_valid = ((x_cnt > h_active) & (x_cnt <= h_backporch)) ? 1'b1 :
1'b0;
assign v_valid = ((y_cnt > v_active) & (y_cnt <= v_backporch)) ? 1'b1 :
1'b0;
assign valid = ((h_valid == 1'b1) & (v_valid == 1'b1)) ? 1'b1 :
1'b0;
assign h_cnt = ((h_valid == 1'b1)) ? x_cnt - 144 :
{10{1'b0}};
assign v_cnt = ((v_valid == 1'b1)) ? y_cnt - 35 :
{10{1'b0}};
endmodule
|
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
|