24C系列的存储器都有这个MEMORY RESET功能吗？

ATMEGA8

查看手册文件，发现有如下一项，可以实现MEMORY RESET功能，
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
请问这个功能包不包括所有的24C系列的存储器？

eblc1388

>> 请问这个功能包不包括所有的24C系列的存储器？

我个人的理解：使用 START 来 RESET I2C BUS 不是24C系列独有的，会适用到所有支恃 I2C 的元件:-

According to the I2C spec:

I2C-bus compatible devices must reset their bus logic
on receipt of a START or repeated START condition
such that they all anticipate the sending of a slave
address, even if these START conditions are not
positioned according to the proper format.

So·a·START condition is basically the same thing as a reset.

The "up to 9 clocks" are needed in case the other device is sending a zero byte
(hence holding SDA low for eight clocks). You don't HAVE to send all 9 clocks,
after each clock you are just looking for SDA to go high.

If SDA doesn't go high after 9 clocks, then something is really screwed up.