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发表于 2013-1-30 11:30:56
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本帖最后由 german010 于 2013-1-30 11:34 编辑
y595906642 发表于 2013-1-30 11:06 ![](static/image/common/back.gif)
基本可以判断不是,
时序约束不好的话可能出现的情况是:
低速跑没问题,时钟速度高了就出错 ...
那应该就是verilog代码写的有问题了
能否帮忙看下 哪里有问题?
1) top模块
uart_rx uart_rx(
.clk(clk_25m),
.key3_rst_n(rst_n),
.rs232_rx(rs232_rx),
.clk_bps(clk_bps_r),
.bps_start(bps_start_r),
//=========
.state0(state0),
.state1(state1),
.state_trg(state_trg),
.test_flg3(test_flg3),
//--------
.setup_en(spi_en_pulse),
.spi_data(spi_data) // 此处为通过 串口接收的 spi需要发送的数据,
);
spi_ctrl spi_ctrl_inst(
.clk(clk_1m_2),
//.clkp(clkp),
// .rst_n(rst_n),
.key4_in(spi_en_pulse),
.spi_data(spi_data),
//---------------------
.sclk(sclk),
.csb(csb),
.mosi(mosi)
);
2) spi 程序 ,其中key4_in已经 改为一个uart接收的命令,使用case语句置为1时 来使能
`timescale 1ns / 1ps
module spi_ctrl(
clk,
// rst_n,
key4_in,//命令spi模块开始发送spi数据
spi_data,//通过 串口接收的spi 数据
sclk, //sclk时钟
csb, //spi总线发送使能,低电平有效
mosi, //spi数据发送端口
);
//
input clk;
//input rst_n;
input key4_in;
output sclk;
output mosi;
input [23:0]spi_data;
reg csb_r;
output csb;
reg [7:0]cnt ;
reg sclk_r;
reg [7:0]mosi_index;
reg clk_r;
always @(posedge clk or negedge key4_in)
begin
if(!key4_in)
begin
cnt <=8'd1;
clk_r <=0;
end
else
begin
if(cnt<=8'd75)
cnt <=cnt+8'd1;
clk_r = ~clk_r;
end
end
//
reg mosi_r;
reg [7:0]num;
always @(posedge clk or negedge key4_in)
if(!key4_in)
csb_r <=1'b0;
else
begin
case (cnt[7:1])
8'd1: begin mosi_r <= spi_data[23];csb_r <=1'b1;end //发送bit0
8'd2: mosi_r <= spi_data[22]; //发送bit1
8'd3: mosi_r <= spi_data[21]; //发送bit2
8'd4: mosi_r <= spi_data[20]; //发送bit3
8'd5: mosi_r <= spi_data[19]; //发送bit4
8'd6: mosi_r <= spi_data[18]; //发送bit5
8'd7: mosi_r <= spi_data[17]; //发送bit6
8'd8: mosi_r <= spi_data[16]; //发送bit7
8'd9: mosi_r <= spi_data[15]; //发送bit0
8'd10: mosi_r <= spi_data[14]; //发送bit1
8'd11: mosi_r <= spi_data[13]; //发送bit2
8'd12: mosi_r <= spi_data[12]; //发送bit3
8'd13: mosi_r <= spi_data[11]; //发送bit4
8'd14: mosi_r <= spi_data[10]; //发送bit5
8'd15: mosi_r <= spi_data[9]; //发送bit6
8'd16: mosi_r <= spi_data[8]; //发送bit7
8'd17: mosi_r <= spi_data[7]; //发送bit0
8'd18: mosi_r <= spi_data[6]; //发送bit1
8'd19: mosi_r <= spi_data[5]; //发送bit2
8'd20: mosi_r <= spi_data[4]; //发送bit3
8'd21: mosi_r <= spi_data[3]; //发送bit4
8'd22: mosi_r <= spi_data[2]; //发送bit5
8'd23: mosi_r <= spi_data[1]; //发送bit6
8'd24: mosi_r <= spi_data[0]; //发送bit7
8'd25: mosi_r <= 1'b0; //发送bit7
8'd35: csb_r <=1'b0;
default:;
endcase
end
//-------------------------------------------------
assign sclk = clk_r && csb_r;
assign mosi = mosi_r;
assign csb = ~csb_r;
endmodule |
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