【求助】state machine 里的condition看不太明白

simpleh · 发表于 2012-11-27 11:47:20

(!current_state).(!current_state).(current_state).(!stb).(always1)
+ (!current_state).(current_state).(!current_state).(!current_state).(!current_state).(!delay_counter[0])
+ (!current_state).(current_state).(!current_state).(!current_state).(!current_state).(delay_counter[0]).(delay_counter[1])
+ (!current_state).(current_state).(!current_state).(!current_state).(current_state).(!delay_counter[0])
+ (!current_state).(current_state).(!current_state).(!current_state).(current_state).(delay_counter[0]).(!delay_counter[1]).(!stb)
+ (!current_state).(current_state).(!current_state).(!current_state).(current_state).(delay_counter[0]).(!delay_counter[1]).(stb).(!ep6_ff)
+ (!current_state).(current_state).(!current_state).(!current_state).(current_state).(delay_counter[0]).(delay_counter[1])
+ (!current_state).(current_state).(!current_state).(current_state)
+ (!current_state).(current_state).(current_state).(!current_state).(!current_state).(!delay_counter[0])
+ (!current_state).(current_state).(current_state).(!current_state).(!current_state).(delay_counter[0]).(!delay_counter[1]).(stb)
+ (!current_state).(current_state).(current_state).(!current_state).(!current_state).(delay_counter[0]).(delay_counter[1])
+ (!current_state).(current_state).(current_state).(!current_state).(current_state)
+ (!current_state).(current_state).(current_state).(current_state)
+ (current_state).(!current_state).(current_state).(!stb).(always1)
+ (current_state).(current_state)

simpleh · 发表于 2012-11-27 11:48:03

simpleh · 发表于 2012-11-27 16:50:35

case(current_state)
S0: //idle
begin
pktend <= 1'B1;
fd_oe <= 1'B0;
sloe <= 1'B1;
slrd <= 1'B1;
slwr <= 1'B1;
delay_counter <= 2'd0;
// timer_start <= 1'B1;
if (stb == 1'B1) // FPGA send ask
begin
if (ep6_ff == 1'B1) //EP6IN
begin
fifoaddr <= 2'B10;
next_state <= S1;
end
end
//else if (ep2_ef==1'B1 && timer_ov==1'B1) //EP2OUT
else if (ep2_ef==1'B1 ) //EP2OUT
begin //接收
fifoaddr <= 2'B00;
next_state <= S4;
end
end
//write
//////////////////////////////////////////////////////////////-
S1: //写FIFO发送数据
begin
sloe <= 1'B0;
slwr <= 1'B0;
fd_oe <= 1'B1;
fd_o <= dat_i;
if (delay_counter == 2'd1)
begin
delay_counter <= 2'd0;
next_state <= S2;
end
else
delay_counter <= delay_counter+1'B1;
end
S2: //slrd active 40ns
begin
sloe <= 1'B1;
slwr <= 1'B1;
if (delay_counter == 2'd2)
begin
delay_counter <= 2'd0;
ack <= 1'B1; // usb receive response
pktend <= 1'B0;
next_state <= S3;
end
else
delay_counter <= delay_counter+1'B1;
end
S3:
begin
if (stb == 1'B0)
begin
ack <= 1'B0;
next_state <= S0;
end
end
//read
//////////////////////////////////////////////////////////////-
S4:
begin
sloe <= 1'B0;
slrd <= 1'B0;
fd_oe <= 1'B0;
if (delay_counter == 2'd1)
begin
delay_counter <= 2'd0;
dat_o <= fd_i;
ntf <= 1'B1; //usb send ask
next_state <= S5;
end
else
delay_counter <= delay_counter+1'B1;
end
S5:
begin
slrd <= 1'B1;
sloe <= 1'B1;
if (delay_counter == 2'd2)
begin
if (nck == 1'B1) //FPGA receive response
begin
ntf <= 1'B0;
delay_counter <= 2'd0;
next_state <= S0;
end
end
else
delay_counter <= delay_counter+1'B1;
end
default:
next_state <= S0;
endcase

复制代码

simpleh · 发表于 2012-11-27 16:51:39

就是这个状态机一直在s4和s5之间循环。s5怎么会跳到s4 呢？想不通！

simpleh · 发表于 2012-11-27 16:58:11

之前贴出来的那个condition就是s5转到s4的

浮云残雪 · 发表于 2012-11-27 18:27:33

simpleh 发表于 2012-11-27 16:51
就是这个状态机一直在s4和s5之间循环。s5怎么会跳到s4 呢？想不通！

先跳到S1再跳到S4

simpleh · 发表于 2012-11-29 10:17:53

浮云残雪发表于 2012-11-27 18:27
先跳到S1再跳到S4

我本来是S0-S4-S5-S0-S1-S2-S3-S0这个顺序，可是仿真的时候就是从S5跳到S4。。就卡住了

浮云残雪 · 发表于 2012-12-1 09:34:12

simpleh 发表于 2012-11-29 10:17
我本来是S0-S4-S5-S0-S1-S2-S3-S0这个顺序，可是仿真的时候就是从S5跳到S4。。就卡住了 ...

不了解了。我抽空再详细看看。

【求助】state machine 里的condition看不太明白

阿莫论坛20周年了！感谢大家的支持与爱护！！

本帖子中包含更多资源