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大家请看一下我的对时钟信号clkc和输入c的判断,判断c放置于判断clkc之前,这样将程序烧入芯片中会有什么问题么?
ps:在modelsim中仿真波形都没问题
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity filter is
port( delayc,c,clkc: in std_logic;
fc : out std_logic);
end entity;
architecture behav of filter is
constant N:integer:=79;
signal countb1,countb2: integer range 0 to N+1;
signal fc1:std_logic;
begin
process(delayc,clkc,c)
begin
if(delayc ='0')then
countb1<=0;
elsif(c='1') then
if(rising_edge(clkc))then
if(countb1<=N) then
countb1<=countb1+1;
else
countb1<=countb1;
end if;
end if;
else
countb1<=0;
end if;
end process;
process(delayc,clkc,c)
begin
if(delayc ='0')then
countb2<=0;
elsif(c='0') then
if(rising_edge(clkc))then
if(countb2<=N) then
countb2<=countb2+1;
else
countb2<=countb2;
end if;
end if;
else
countb2<=0;
end if;
end process;
process(delayc,clkc)
begin
if(delayc ='0')then
fc1<='0';
fc<='0';
elsif (rising_edge(clkc)) then
if(countb1>=N) then
fc1<='1';
elsif(countb2>=N) then
fc1<='0';
else
fc1<=fc1;
end if;
end if;
fc<=fc1;
end process;
end behav;
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阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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