频率计，将测试信号关闭后数码管竟然不显示0，怎么回事？

orange-208 · 发表于 2012-10-11 17:21:27

RT，效果应该是信号发生器给多少Hz的信号，数码管应该显示多少，问题是，每次只能测第一次给的信号，信号改变之后数码管没变化，并且信号断掉之后，数码管仍然显示第一测试的信号，怎么回事？？

高手？、留步？

orange-208 · 发表于 2012-10-11 17:22:03

撕心裂肺的求助！！！1

hackerboygn · 发表于 2012-10-11 17:38:00

什么神器频率计啊？

门时间设的太长了？

ckvlhf · 发表于 2012-10-11 17:57:31

DIY的？程序最后一行是while（1）；？

jlhgold · 发表于 2012-10-11 18:00:09

你应该把代码贴出来，说不定有高手会看看的！

orange-208 · 发表于 2012-10-11 19:31:11

附上代码：

module Counter
(
CLK, Clear, Sig_in,
Enable_0, Switch,

Cnt_data1, Cnt_data2
// Count_over
);

input CLK, Clear;
input Sig_in, Enable_0, Switch;

output [31:0]Cnt_data1, Cnt_data2;
// output reg Count_over;

/********************************************/

parameter Freq_100KHz = 17'd100_000, //Fs = 100,000

Ns0 = 14'd9_999; //Ns0 = 10,000

/****************** 被测信号 *****************/

reg [31:0]count1 =32'd0, count2 = 32'd0;

reg trigger = 1'b0;

reg [13:0]Sig_num = 14'd0;

reg Sig_flag;

always @ ( posedge Sig_in )
if( Clear == 1'b1 )
begin
count1 <= 32'd0;
Sig_flag <= 1'b0;
// Count_over <= 1'b0;
end
else if( Enable_0 )
begin
if( Switch == 1'b1 && count1 <= Sig_num )
begin
trigger <= 1'b1;
count1 <= count1 + 1'b1;
Sig_flag <= 1'b1;
end
else
begin
trigger <= 1'b0;
count1 <= count1;
Sig_flag <= 1'b0;
// Count_over <= 1'b1; //count_over结束计数标志
end
end

/****************** 标准信号 *****************/

always @ ( posedge CLK )
begin
if( Clear == 1'b1 )
begin
count2 <= 32'd0;
end
else
begin
if( trigger == 1'b1 )
begin
count2 <= count2 + 1'b1;
end
else
begin
count2 <= count2;
end
end
end

/********************************************/

always @ ( posedge CLK )
begin
if( Clear == 1'b1 )
begin
Sig_num <= 14'd0;
end
else
begin
if( ( count2 < Ns0 ) && ( Sig_flag == 1'b1 ) )
begin
Sig_num <= Sig_num + 1'b1;
end
else
begin
Sig_num <= Sig_num;
end
end
end

/********************************************/

assign Cnt_data1 = count1 * Freq_100KHz;

assign Cnt_data2 = count2;

/********************************************/

endmodule

orange-208 · 发表于 2012-10-11 19:31:41

上面这个是计数的模块

orange-208 · 发表于 2012-10-11 19:32:17

module Contral
(
CLK,
RSTn,
Start, //Trigger signal

// Count_over,
Div_over,
BCD_over,

Clear, //Control counter cleared
Switch, //Control counter gate signal
Enable_0, //Enable the counter
Enable_1, //Enable  BCD code conversion
Enable_2 //Enable the Division
);

input CLK, RSTn;
input Start, Div_over, BCD_over; //Count_over,

output Enable_0, Enable_1, Enable_2, Clear, Switch;

wire Start, Div_over, BCD_over; //Count_over,
reg  Enable_0, Enable_1, Enable_2, Clear, Switch;

/*************************************************************/

parameter Wait = 5'b00001,
Count  = 5'b00010,
Divide = 5'b00100,
BinBCD = 5'b01000,
Led = 5'b10000;

/*************************************************************/

reg [4:0]Current_state , Next_state;

always @ ( posedge CLK or negedge RSTn )
begin
if( !RSTn )
Current_state <= Count;
else
Current_state <= Next_state;
end

always @ ( Start or Current_state or Div_over or BCD_over or RSTn )
begin
case( Current_state )
Wait:
begin
//----Start，默认为1,执行Count使Switch=1，闸门信号开，开始计数。
Next_state = ( Start ) ? Count : Wait;
end

Count:
begin
Next_state = ( !Start ) ? Divide : Count;
end

Divide:
begin
Next_state = ( !Div_over ) ? Divide : BinBCD;
end

BinBCD:
begin
Next_state = ( !BCD_over ) ? BinBCD : Led;
end

Led:
begin
Next_state = ( RSTn ) ? Wait : Led;
end
endcase
end

always @ ( Current_state )
begin
case( Current_state )
Wait:
begin
Enable_2 = 1'b0;
Enable_1 = 1'b0;
Enable_0 = 1'b0;
Switch = 1'b0;
Clear = 1'b1;
end

Count:
begin
Enable_2 = 1'b0;
Enable_1 = 1'b0;
Enable_0 = 1'b1;
Switch = 1'b1;
Clear = 1'b0;
end

Divide:
begin
Enable_2 = 1'b1;
Enable_1 = 1'b0;
Enable_0 = 1'b0;
Switch = 1'b0;
Clear = 1'b0;
end

BinBCD:
begin
Enable_2 = 1'b0;
Enable_1 = 1'b1;
Enable_0 = 1'b0;
Switch = 1'b0;
Clear = 1'b0;
end

Led:
begin
Enable_2 = 1'b0;
Enable_1 = 1'b0;
Enable_0 = 1'b0;
Switch = 1'b0;
Clear = 1'b0;
end
endcase
end

/*************************************************************/

endmodule

频率计，将测试信号关闭后数码管竟然不显示0，怎么回事？

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