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![](static/image/common/ico_lz.png)
楼主 |
发表于 2012-10-11 15:19:29
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附上Verilog代码
module Counter
(
CLK, Clear,
Sig_in, Switch,
Cnt_data1, Cnt_data2
);
input CLK, Clear;
input Sig_in, Switch;
output [31:0]Cnt_data1, Cnt_data2;
/********************************************/
parameter Freq_100KHz = 17'd100_000, //Fs = 100,000
Ns0 = 14'd9_999; //Ns0 = 10,000
/****************** 被测信号 *****************/
reg [31:0]count1 =32'd0, count2 = 32'd0;
reg trigger = 1'b0;
reg [13:0]Sig_num = 14'd0;
reg Sig_flag;
always @ ( posedge Sig_in )
begin
if( Clear == 1'b1 )
begin
count1 <= 32'd0;
Sig_flag <= 1'b0;
end
else if( Switch == 1'b1 && count1 <= Sig_num )
begin
trigger <= 1'b1;
count1 <= count1 + 1'b1;
Sig_flag <= 1'b1;
end
else
begin
trigger <= 1'b0;
count1 <= count1;
Sig_flag <= 1'b0;
end
end
/****************** 标准信号 *****************/
always @ ( posedge CLK )
begin
if( trigger == 1'b1 )
count2 <= count2 + 1'b1;
else
count2 <= count2;
end
/********************************************/
always @ ( posedge CLK )
begin
if( ( count2 < Ns0 ) && ( Sig_flag == 1'b1 ) )
begin
Sig_num <= Sig_num + 1'b1;
end
else
begin
Sig_num <= Sig_num;
end
end
/********************************************/
assign Cnt_data1 = count1 * Freq_100KHz;
assign Cnt_data2 = count2;
/********************************************/
endmodule |
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