求解一段verilog代码

flyriz · 发表于 2012-9-18 09:25:48

本帖最后由 flyriz 于 2012-9-18 09:27 编辑

//按键记数，数码管动态显示，两位
//

module test(clk,key,dispcode,CS);
input clk,key;
output reg [6:0] dispcode = N0;
output reg [1:0]CS;
reg [6:0]num;
reg [3:0]num_t;
reg [19:0]count1;
reg [7:0]count2;
reg timeflag;
reg keyflag = 1,lastkeyflag=1; // 1 up ,0 down

/* 共阴极 :不带小数点
0,  1,  2,  3,  4,  5,  6,  7,
3fh,06h,5bh,4fh,66h,6dh,7dh,07h
8,  9,
7fh,6fh,00h*/
parameter N0  = 7'h3f,
N1  = 7'h06,
N2  = 7'h5b,
N3  = 7'h4f,
N4  = 7'h66,
N5  = 7'h6d,
N6  = 7'h7d,
N7  = 7'h07,
N8  = 7'h7f,
N9  = 7'h6f,
N10 = 7'h77;

always @(posedge clk)
begin
if(count1 < 20'd500000)  //10ms
count1 = count1+1'd1;
else
begin
count1=0;
if(count2 < 1) //
count2=count2+1'd1;
else
begin
count2=0;
timeflag = ~timeflag; //每10ms翻转一次
end
end
end

always @(posedge timeflag)  //延时去抖动
begin
if(lastkeyflag==0 && key == 0)
keyflag = 0;
if(lastkeyflag==1 && key == 1)
keyflag = 1;

lastkeyflag = key;
end

always @(negedge keyflag)
begin
num <= num + 1'd1; //对num的赋值必须用=，不能用<= ，否则num的值会显示100;而且必须统一
if(num>99)
num <= 0;
end

always @(posedge timeflag) //数码管动态显示
begin
CS = CS + 1;
if(CS > 2'd2)
CS = 2'd1;

if(CS==2'd1)
num_t = num%10;
if(CS==2'd2)
num_t = num/10;
case(num_t)
4'd0 : dispcode = N0;
4'd1 : dispcode = N1;
4'd2 : dispcode = N2;
4'd3 : dispcode = N3;
4'd4 : dispcode = N4;
4'd5 : dispcode = N5;
4'd6 : dispcode = N6;
4'd7 : dispcode = N7;
4'd8 : dispcode = N8;
4'd9 : dispcode = N9;
4'd10: dispcode = N10;
default: dispcode = 7'h40;
endcase
end

endmodule

问题：
always @(posedge timeflag) //数码管动态显示
这条语句如果改成 always @(timeflag) 就不对了，timeflag我设置的是10ms翻转一次，改完之后应该动态扫描的频率更快了才对啊？
哪位大神指导一下，谢谢！

jathenal · 发表于 2012-9-18 13:38:48

电平触发和沿触发不能等效吧
按你提速的想法貌似应该为posedge timeflag | negedge timeflag，而不是直接的timeflag

flyriz · 发表于 2012-9-18 14:03:16

jathenal 发表于 2012-9-18 13:38
电平触发和沿触发不能等效吧
按你提速的想法貌似应该为posedge timeflag | negedge timeflag，而不是直接的 ...

//数码管静态循环显示

module seg(clk,num1,CS);
input clk;
output reg [6:0] num1 = N0;
output [1:0]CS;
reg [3:0]count;
reg [19:0]count1;
reg [7:0]count2;
reg timeflag;

/*       共阴极 :不带小数点
0,  1,  2,  3,  4,  5,  6,  7,
3fh,06h,5bh,4fh,66h,6dh,7dh,07h
8,  9,
7fh,6fh,00h*/
parameter       N0       = 7'h3f,
                     N1       = 7'h06,
                     N2       = 7'h5b,
                     N3       = 7'h4f,
                     N4       = 7'h66,
                     N5       = 7'h6d,
                     N6       = 7'h7d,
                     N7       = 7'h07,
                     N8       = 7'h7f,
                     N9       = 7'h6f;
parameter       tvalue = 100;


always @(posedge clk)
      begin
            if(count1 < 20'd500000)
                     count1 = count1+1'd1;
            else
                     begin
                              count1=0;
                              if(count2<tvalue)
                                    count2=count2+1'd1;
                              else
                                    begin
                                             count2=0;
                                             timeflag = 1'd1;
                                    end
                     end

            if(timeflag)
                     begin
                              timeflag = 0;
                              count = count + 1'd1;
                              if(count>9)
                                    count = 0;
                     end
      end

always @(count)
      begin
            case(count)
                     4'd0: num1 = N0;
                     4'd1: num1 = N1;
                     4'd2: num1 = N2;
                     4'd3: num1 = N3;
                     4'd4: num1 = N4;
                     4'd5: num1 = N5;
                     4'd6: num1 = N6;
                     4'd7: num1 = N7;
                     4'd8: num1 = N8;
                     4'd9: num1 = N9;
                     default: num1 = 7'h40;
            endcase
      end

      assign CS = 2'd1;
endmodule
我用这段代码又是正常的，我这里也是这么用的啊：always @(count)

jlhgold · 发表于 2012-9-18 20:36:55

好像是这样的吧
count是个数范围是0-9 所以可以
timeflag是个标志位范围是0和1

mysunmax · 发表于 2012-9-18 21:42:17

本帖最后由 mysunmax 于 2012-9-18 21:43 编辑

always @(posedge timeflag)       //数码管动态显示
      begin
            CS = CS + 1;
            if(CS > 2'd2)
                     CS = 2'd1;

            if(CS==2'd1)
                     num_t = num%10;
            if(CS==2'd2)
                     num_t = num/10;
            case(num_t)
                     4'd0 : dispcode = N0;
                     4'd1 : dispcode = N1;
                     4'd2 : dispcode = N2;
                     4'd3 : dispcode = N3;
                     4'd4 : dispcode = N4;
                     4'd5 : dispcode = N5;
                     4'd6 : dispcode = N6;
                     4'd7 : dispcode = N7;
                     4'd8 : dispcode = N8;
                     4'd9 : dispcode = N9;
                     4'd10: dispcode = N10;
            default: dispcode = 7'h40;
            endcase
      end

endmodule
这段代码有问题~~  always @(timeflag)    CS = CS + 1;  组合语句中出现这样的语句会是什么样子？

pengxin213 · 发表于 2012-9-18 21:57:16

时序电路中最好用非阻塞赋值<=，比如楼上所说的就是个大问题啊

今世小浪子 · 发表于 2012-9-20 15:21:36

flyriz 发表于 2012-9-18 14:03
//数码管静态循环显示

module seg(clk,num1,CS);

建议你去看看电平触发和边沿触发的知识

今世小浪子 · 发表于 2012-9-20 15:23:12

mysunmax 发表于 2012-9-18 21:42
always @(posedge timeflag)       //数码管动态显示
      begin
            CS = CS + 1;

把 CS = CS + 1 改成 <= 非阻塞

求解一段verilog代码

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