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module tryfunct(clk,reset,n,result);
input reset,clk;
input [3:0] n;
output [31:0] result;
reg [31:0] result;
always@(posedge clk)
begin
if(!reset)
result<=0;
else
begin
result<=n*factorial(n)/((n*2)+1);
end
end
function [31:0] factorial;
input [3:0] operand;
reg [3:0] index;
begin
factorial=operand?1:0;
for(index=2;index<=operand;index=index+1)
factorial=index*factorial;
end
endfunction
endmodule
报错是:
Error (10119): Verilog HDL Loop Statement error at tryfunct.v(21): loop with non-constant loop condition must terminate within 250 iterations
Error (10903): Verilog HDL error at tryfunct.v(12): failed to elaborate task or function "factorial"
Error: Can't elaborate top-level user hierarchy
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阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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