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![](static/image/common/ico_lz.png)
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发表于 2012-7-24 22:32:04
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/************************************************************************************************************************************************************************************************
Using Internal Oscillator in MAX V
Jan 2010
************************************************************************************************************************************************************************************************/
// Top Level module
`timescale 1 ps / 1 ps
module int_osc (pb0, led , osc, clk);
/**********************************************************************************************************
pb0 : To control the enable signal of the internal oscillator, assigned to pin M9
osc : Output from internal oscillator, assigned to pin M4
clk : osc/(2^21), assigned to pin P2
led[1:0] : Blinking leds to demostrate the functionality of internal oscillator, assigned to pin R1 and P4
**********************************************************************************************************/
/* Input is push button switch and outputs are leds */
input pb0;
output clk, osc;
output[1:0] led;
wire osc_w, oscena_w, clk_w;
wire [1:0] led_w;
assign oscena_w =(pb0); // Enable the oscillator
assign osc = osc_w;
assign clk= clk_w;
assign led=~led_w;
counter cntr (.ct_out(led_w), .clk(clk_w));
altufm_osc0_altufm_osc_1p3 ufm (.osc(osc_w), .oscena(oscena_w));
reduced_osc rosc (.osc(osc_w), .clk(clk_w));
endmodule
/***********************************************************************************************************************************************************************************************
Module for displaying running LED pattern
**************************************************************************************************************************/
module counter (clk, ct_out);
/* Input is the output of the reduced oscillator module
* Outputs are the blinking LEDs*/
input clk;
output[1:0] ct_out;
reg [1:0] ct_out;
initial
begin
ct_out= 0;
end
always @ (posedge clk) begin
ct_out <= ct_out + 1'b1;
end
endmodule
/**************************************************************************************************************************************************/
/* Megafunction for Internal oscillator */
`timescale 1 ps / 1 ps
//synopsys translate_on
module altufm_osc0_altufm_osc_1p3
(
osc,
oscena) /* synthesis synthesis_clearbox=1 */;
output osc;
input oscena;
wire wire_maxv_ufm_block1_osc;
maxv_ufm maxv_ufm_block1
(
.arclk(1'b0),
.ardin(1'b0),
.arshft(1'b0),
.bgpbusy(),
.busy(),
.drclk(1'b0),
.drdout(),
.drshft(1'b0),
.osc(wire_maxv_ufm_block1_osc),
.oscena(oscena)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.drdin(1'b0),
.erase(1'b0),
.program(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.ctrl_bgpbusy(),
.devclrn(),
.devpor(),
.sbdin(),
.sbdout()
// synopsys translate_on
);
defparam
maxv_ufm_block1.address_width = 9,
maxv_ufm_block1.osc_sim_setting = 500000,
maxv_ufm_block1.lpm_type = "maxv_ufm";
assign
osc = wire_maxv_ufm_block1_osc;
endmodule //altufm_osc0_altufm_osc_1p3
//VALID FILE
/****************************************************************************************************************************
Module to reduce the frequency of internal oscillator
****************************************************************************************************************************/
module reduced_osc (osc, clk);
input osc; // Output of internal osc
output clk; // Reduced frequency clock
reg [25:0] count;
reg clk;
initial
begin
count = 0;
end
always @ (posedge osc) begin
count <= count + 1;
clk <= count[20];
end
endmodule
/***************************************************************************************************************************/
官方代码 中间的模块 module altufm_osc0_altufm_osc_1p3 是什么作用呀, |
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