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发表于 2012-7-4 10:11:05
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你的FIFO没写好吧。我给你个我写的通用FIFO程序:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:06:33 04/08/2012
// Design Name:
// Module Name: BlockRamFIFOx16
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BlockRamFIFO256x16(
input int_in_GCLK,
input int_in_GRST,
input [15:0] int_in_PortA_in,
input int_in_PortA_WE_in, // Active 1
output int_out_PortA_Full,
output [15:0] int_out_PortB_out,
output int_out_PortB_out_DRDY,
input int_in_PortB_RD_in, // Active 1
output int_out_PortB_Empty
);
reg [8:0] r_Addr_int_in_PortA_in;
reg r_PortA_WE;
reg [15:0] r_int_in_PortA_in;
reg [8:0] r_Addr_int_out_PortB_out;
reg [15:0] r_int_out_PortB_out;
wire [15:0] w_PortB_out;
reg r_int_out_PortB_out_DRDY;
assign int_out_PortB_out = r_int_out_PortB_out;
assign int_out_PortB_out_DRDY = r_int_out_PortB_out_DRDY;
wire w_FIFOEmpty = (r_Addr_int_in_PortA_in == r_Addr_int_out_PortB_out);
wire w_FIFOFull = (r_Addr_int_in_PortA_in == {~r_Addr_int_out_PortB_out[8],r_Addr_int_out_PortB_out[7:0]});
assign int_out_PortA_Full = w_FIFOFull;
assign int_out_PortB_Empty = w_FIFOEmpty;
reg [1:0] r_int_in_PortB_RD_in_delay;
always @(posedge int_in_GCLK or negedge int_in_GRST)
begin
if(~int_in_GRST)
begin
r_Addr_int_in_PortA_in <= 0;
r_Addr_int_out_PortB_out <= 0;
r_PortA_WE <= 0;
end
else
begin
if(int_in_PortA_WE_in & ~w_FIFOFull)
begin
// Address inc first, then write
r_int_in_PortA_in <= int_in_PortA_in;
r_Addr_int_in_PortA_in <= r_Addr_int_in_PortA_in + 1;
r_PortA_WE <= 1;
end
else
begin
r_PortA_WE <= 0;
end
r_int_in_PortB_RD_in_delay <= {r_int_in_PortB_RD_in_delay[0],int_in_PortB_RD_in};
if(r_int_in_PortB_RD_in_delay[1])
begin
r_int_out_PortB_out_DRDY <= 1;
r_int_out_PortB_out <= w_PortB_out;
end
else
begin
r_int_out_PortB_out_DRDY <= 0;
r_int_out_PortB_out <= r_int_out_PortB_out;
end
if(int_in_PortB_RD_in & ~w_FIFOEmpty)
begin
// Address inc first, then read after 1 cycle
r_Addr_int_out_PortB_out <= r_Addr_int_out_PortB_out + 1;
end
else
begin
r_Addr_int_out_PortB_out <= r_Addr_int_out_PortB_out;
end
end
end
RAMB4_S16_S16 RAMS16FIFOAIBO(
.DIA(r_int_in_PortA_in), // Port A 8-bit data input
.WEA(r_PortA_WE), // Port A RAM write enable input
.DOB(w_PortB_out), // Port B 8-bit data output
.ADDRA(r_Addr_int_in_PortA_in[7:0]), // Port A 9-bit address input
.ADDRB(r_Addr_int_out_PortB_out[7:0]), // Port B 9-bit address input
.CLKA(int_in_GCLK), // Port A clock input
.CLKB(int_in_GCLK), // Port B clock input
.ENA(1'b1), // Port A RAM enable input
.ENB(1'b1), // Port B RAM enable input
.RSTA(1'b0), // Port A Synchronous reset input
.RSTB(1'b0), // Port B Synchronous reset input
.WEB(1'b0)// Port B RAM write enable input
);
endmodule
我的片子只有4Kb的小块,老片子,新的可以照改,只要保证地址位宽等等一致就行了。注意我这是同步FIFO。异步的我还没搞,不容易搞。 |
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