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前几天我做了个测试，因为使用的FPGA芯片有个别引脚坏的情况，为了验证引脚的好坏，我给所有引脚同时灌输一个波形，可没想到下载这个程序之后就再也下不进程序，芯片也不能工作了，
我又连续试了三块芯片，三块都出现了同样的情况，下载后每个引脚上都是这个波形（如下图），出现脉宽为415ns的低电平，幸好这些芯片我都是从公司其余废板子上拆下的，现在把源码跟
编译后的结果贴在下面，大家一起来研究下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test_pin is
generic (n:natural:=8);
port(
clk:in std_logic;
pin:buffer std_logic_vector(31 downto 0);
pin1:buffer std_logic_vector(31 downto 0);
pin2:buffer std_logic_vector(8 downto 0)
);
end test_pin;
architecture rtl of test_pin is
begin
process(clk)
variable num:integer range 0 to n;
begin
if clk'event and clk='1'then
if num=n then
pin<=not pin;
pin1<=not pin1;
pin2<=not pin2;
num:=0;
else
num:=num+1;
end if;
end if;
end process;
end rtl;
Design Summary:
Number of PFU registers: 45
Number of SLICEs: 24 out of 320 (8%)
SLICEs(logic/ROM): 24 out of 128 (19%)
SLICEs(logic/ROM/RAM): 0 out of 192 (0%)
As RAM: 0
As Logic/ROM: 0
Number of logic LUT4s: 46
Number of distributed RAM: 0 (0 LUT4s)
Number of ripple logic: 0 (0 LUT4s)
Number of shift registers: 0
Total number of LUT4s: 46
Number of external PIOs: 74 out of 74 (100%)
Number of 3-state buffers: 0
Number of GSRs: 0 out of 1 (0%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Number of TSALL: 0 out of 1 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 1
Net clk_c: 24 loads, 24 rising, 0 falling (Driver: PIO clk )
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阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2012-4-28 13:35:50
楼主
