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发表于 2012-5-5 16:23:48
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你好,我现在也在研究k60的SD卡开发,用的也是SPI,但是我的SD卡初始化一直不能进入idle模式,下面是我的SPI初始化部分程序,能不能帮我看下有什么问题,或者给我提供一些建议,不胜感激。- void spi_init(uint8_t spino, uint8_t master)
- {
- SPI_MemMapPtr base_addr = spi_get_base_address(spino);
-
- /* 使能SPI模块时钟,配置SPI引脚功能 */
- if(SPI_MOD_SET(spino) == SPI0)
- {
- SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;
-
- /* PORT_PCR_MUX(0x2) : SPI功能
- * PORT_PCR_DSE_MASK : Drive Strength Enable */
- gpio_init(0, 13, OUT_PUT, 1); /* PCS0 */
- PORTA_PCR15 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
- PORTA_PCR16 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
- PORTA_PCR17 = 0 | PORT_PCR_MUX(0x2); /* SIN */
- }
- else if(SPI_MOD_SET(spino) == SPI1)
- {
- SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
- PORTE_PCR4 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* PCS0 */
- PORTE_PCR2 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
- PORTE_PCR1 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
- PORTE_PCR3 = 0 | PORT_PCR_MUX(0x2); /* SIN */
- }
- else
- {
- SIM_SCGC3 |= SIM_SCGC3_SPI2_MASK;
- }
-
- SPI_MCR_REG(base_addr) = 0
- | SPI_MCR_CLR_TXF_MASK /* Clear the Tx FIFO counter. */
- | SPI_MCR_CLR_RXF_MASK /* Clear the Rx FIFO counter. */
- | SPI_MCR_PCSIS_MASK /* Peripheral Chip Select x Inactive State */
- | SPI_MCR_HALT_MASK; /* Starts and stops DSPI transfers */
- /* 根据主从机模式设置工作模式 */
- if(master == MASTER)
- {
- SPI_MCR_REG(base_addr) |= SPI_MCR_MSTR_MASK; /* Master/Slave Mode Select */
- SPI_CTAR_REG(base_addr,0) = 0
- | SPI_CTAR_DBR_MASK /* Double Baud Rate */
- | SPI_CTAR_FMSZ(0x08) /* Frame Size */
- | SPI_CTAR_PDT_MASK /* 延时因子为7 */
- | SPI_CTAR_BR(0x8) /* Selects the scaler value for the baud rate. */
- | SPI_CTAR_CPOL_MASK /* Clock Polarity:The inactive state value of SCK is high */
- | SPI_CTAR_CPHA_MASK; /* Clock Phase:Data is changed on the leading edge of SCK */
- }
- else
- {
- SPI_CTAR_SLAVE_REG(base_addr,0) = 0
- | SPI_CTAR_SLAVE_FMSZ(0x08)
- | SPI_CTAR_SLAVE_CPOL_MASK
- | SPI_CTAR_SLAVE_CPHA_MASK;
- }
-
- SPI_SR_REG(base_addr) = (SPI_SR_EOQF_MASK /* End of Queue Flag */
- | SPI_SR_TFUF_MASK /* Transmit FIFO Underflow Flag */
- | SPI_SR_TFFF_MASK /* Transmit FIFO Fill Flag */
- | SPI_SR_RFOF_MASK /* Receive FIFO Overflow Flag */
- | SPI_SR_RFDF_MASK); /* Receive FIFO Drain Flag */
-
- SPI_MCR_REG(base_addr) &= ~SPI_MCR_HALT_MASK; /* start */
-
- }
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