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楼主 |
发表于 2012-4-13 19:44:10
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#include <MSP430x14x.h>
// Configuration Registers
#define CC1101_IOCFG2 0x00 // GDO2 output pin configuration
#define CC1101_IOCFG1 0x01 // GDO1 output pin configuration
#define CC1101_IOCFG0 0x02 // GDO0 output pin configuration
#define CC1101_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CC1101_SYNC1 0x04 // Sync word, high byte
#define CC1101_SYNC0 0x05 // Sync word, low byte
#define CC1101_PKTLEN 0x06 // Packet length
#define CC1101_PKTCTRL1 0x07 // Packet automation control
#define CC1101_PKTCTRL0 0x08 // Packet automation control
#define CC1101_ADDR 0x09 // Device address
#define CC1101_CHANNR 0x0A // Channel number
#define CC1101_FSCTRL1 0x0B // Frequency synthesizer control
#define CC1101_FSCTRL0 0x0C // Frequency synthesizer control
#define CC1101_FREQ2 0x0D // Frequency control word, high byte
#define CC1101_FREQ1 0x0E // Frequency control word, middle byte
#define CC1101_FREQ0 0x0F // Frequency control word, low byte
#define CC1101_MDMCFG4 0x10 // Modem configuration
#define CC1101_MDMCFG3 0x11 // Modem configuration
#define CC1101_MDMCFG2 0x12 // Modem configuration
#define CC1101_MDMCFG1 0x13 // Modem configuration
#define CC1101_MDMCFG0 0x14 // Modem configuration
#define CC1101_DEVIATN 0x15 // Modem deviation setting
#define CC1101_MCSM2 0x16 // Main Radio Cntrl State Machine config
#define CC1101_MCSM1 0x17 // Main Radio Cntrl State Machine config
#define CC1101_MCSM0 0x18 // Main Radio Cntrl State Machine config
#define CC1101_FOCCFG 0x19 // Frequency Offset Compensation config
#define CC1101_BSCFG 0x1A // Bit Synchronization configuration
#define CC1101_AGCCTRL2 0x1B // AGC control
#define CC1101_AGCCTRL1 0x1C // AGC control
#define CC1101_AGCCTRL0 0x1D // AGC control
#define CC1101_WOREVT1 0x1E // High byte Event 0 timeout
#define CC1101_WOREVT0 0x1F // Low byte Event 0 timeout
#define CC1101_WORCTRL 0x20 // Wake On Radio control
#define CC1101_FREND1 0x21 // Front end RX configuration
#define CC1101_FREND0 0x22 // Front end TX configuration
#define CC1101_FSCAL3 0x23 // Frequency synthesizer calibration
#define CC1101_FSCAL2 0x24 // Frequency synthesizer calibration
#define CC1101_FSCAL1 0x25 // Frequency synthesizer calibration
#define CC1101_FSCAL0 0x26 // Frequency synthesizer calibration
#define CC1101_RCCTRL1 0x27 // RC oscillator configuration
#define CC1101_RCCTRL0 0x28 // RC oscillator configuration
#define CC1101_FSTEST 0x29 // Frequency synthesizer cal control
#define CC1101_PTEST 0x2A // Production test
#define CC1101_AGCTEST 0x2B // AGC test
#define CC1101_TEST2 0x2C // Various test settings
#define CC1101_TEST1 0x2D // Various test settings
#define CC1101_TEST0 0x2E // Various test settings
// Strobe commands
#define CC1101_SRES 0x30 // Reset chip.
#define CC1101_SFSTXON 0x31 // Enable/calibrate freq synthesizer
#define CC1101_SXOFF 0x32 // Turn off crystal oscillator.
#define CC1101_SCAL 0x33 // Calibrate freq synthesizer & disable
#define CC1101_SRX 0x34 // Enable RX.
#define CC1101_STX 0x35 // Enable TX.
#define CC1101_SIDLE 0x36 // Exit RX / TX
#define CC1101_SAFC 0x37 // AFC adjustment of freq synthesizer
#define CC1101_SWOR 0x38 // Start automatic RX polling sequence
#define CC1101_SPWD 0x39 // Enter pwr down mode when CSn goes hi
#define CC1101_SFRX 0x3A // Flush the RX FIFO buffer.
#define CC1101_SFTX 0x3B // Flush the TX FIFO buffer.
#define CC1101_SWORRST 0x3C // Reset real time clock.
#define CC1101_SNOP 0x3D // No operation.
// Status registers
#define CC1101_PARTNUM 0x30 // Part number
#define CC1101_VERSION 0x31 // Current version number
#define CC1101_FREQEST 0x32 // Frequency offset estimate
#define CC1101_LQI 0x33 // Demodulator estimate for link quality
#define CC1101_RSSI 0x34 // Received signal strength indication
#define CC1101_MARCSTATE 0x35 // Control state machine state
#define CC1101_WORTIME1 0x36 // High byte of WOR timer
#define CC1101_WORTIME0 0x37 // Low byte of WOR timer
#define CC1101_PKTSTATUS 0x38 // Current GDOx status and packet status
#define CC1101_VCO_VC_DAC 0x39 // Current setting from PLL cal module
#define CC1101_TXBYTES 0x3A // Underflow and # of bytes in TXFIFO
#define CC1101_RXBYTES 0x3B // Overflow and # of bytes in RXFIFO
#define CC1101_NUM_RXBYTES 0x7F // Mask "# of bytes" field in _RXBYTES
// Other memory locations
#define CC1101_PATABLE 0x3E
#define CC1101_TXFIFO 0x3F
#define CC1101_RXFIFO 0x3F
// Masks for appended status bytes
#define CC1101_LQI_RX 0x01 // Position of LQI byte
#define CC1101_CRC_OK 0x80 // Mask "CRC_OK" bit within LQI byte
// Definitions to support burst/single access:
#define CC1101_WRITE_BURST 0x40
#define CC1101_READ_SINGLE 0x80
#define CC1101_READ_BURST 0xC0
/*
#define CC1101_LED_PxOUT P1OUT
#define CC1101_LED_PxDIR P1DIR
#define CC1101_LED1 0x01
#define CC1101_LED2 0x02
#define CC1101_LED3 0x04
#define CC1101_LED4 0x08
#define CC1101_SW_PxIN P1IN
#define CC1101_SW_PxIE P1IE
#define CC1101_SW_PxIES P1IES
#define CC1101_SW_PxIFG P1IFG
#define CC1101_SW1 0x10
#define CC1101_SW2 0x20
#define CC1101_SW3 0x40
#define CC1101_SW4 0x80
*/
void CC1101_UART_SPISetup(void);
void CC1101_PowerupReset(void);
void CC1101_SPIWriteReg(char, char);
void CC1101_SPIWriteBurstReg(char, char*, char);
char CC1101_SPIReadReg(char);
void CC1101_SPIReadBurstReg(char, char *, char);
char CC1101_SPIReadStatus(char);
void CC1101_SPIStrobe(char);
void CC1101_Wait(unsigned int);
void Delayms(unsigned int delay) ;
void CC1101_Write_Settings(void);
void CC1101_SendPacket(char *txBuffer, char size);
char CC1101_ReceivePacket(char *rxBuffer, char *length);
char paTable[8] = {0x8E,0x8E,0x8E,0x8E,0x8E,0x8E,0x8E,0x8E};
char paTableLen = 8;
#define CC1101_GDO0_PxOUT P1OUT
#define CC1101_GDO0_PxIN P1IN
#define CC1101_GDO0_PxDIR P1DIR
#define CC1101_GDO0_PxIE P1IE
#define CC1101_GDO0_PxIES P1IES
#define CC1101_GDO0_PxIFG P1IFG
#define CC1101_GDO0_PIN BIT5
#define CC1101_GDO2_PxOUT P1OUT
#define CC1101_GDO2_PxIN P1IN
#define CC1101_GDO2_PxDIR P1DIR
#define CC1101_GDO2_PIN BIT6
#define CC1101_CSn_PxOUT P5OUT
#define CC1101_CSn_PxDIR P5DIR
#define CC1101_CSn_PIN BIT0
#define CC1101_SPI_USART1_PxSEL P5SEL
#define CC1101_SPI_USART1_PxDIR P5DIR
#define CC1101_SPI_USART1_PxIN P5IN
#define CC1101_SPI_USART1_SIMO BIT1
#define CC1101_SPI_USART1_SOMI BIT2
#define CC1101_SPI_USART1_UCLK BIT3
void CC1101_Wait(unsigned int cycles)
{
while(cycles>15) // 15 cycles consumed by overhead
cycles = cycles - 6; // 6 cycles consumed each iteration
}
void CC1101_UART_SPISetup(void)
{
CC1101_CSn_PxOUT |= CC1101_CSn_PIN;
CC1101_CSn_PxDIR |= CC1101_CSn_PIN; // /CS disable
ME2 |= USPIE1; // Enable USART1 SPI mode
UCTL1 |= CHAR + SYNC + MM; // 8-bit SPI Master **SWRST**
UTCTL1 |= CKPL + SSEL1 + SSEL0 + STC; // SMCLK, 3-pin mode
UBR01 = 0x02; // UCLK/2
UBR11 = 0x00; // 0
UMCTL1 = 0x00; // No modulation
CC1101_SPI_USART1_PxSEL |= CC1101_SPI_USART1_SIMO | CC1101_SPI_USART1_SOMI | CC1101_SPI_USART1_UCLK;
// SPI option select
CC1101_SPI_USART1_PxDIR |= CC1101_SPI_USART1_SIMO + CC1101_SPI_USART1_UCLK;
// SPI TXD out direction
UCTL1 &= ~SWRST; // Initialize USART state machine
}
void CC1101_SPIWriteReg(char addr, char value)
{
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag??
U1TXBUF = addr; // Send address
while (!(IFG2&URXIFG1)); // Wait for TX to finish??
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = value; // Load data for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of addr TX??
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
}
void CC1101_SPIWriteBurstReg(char addr, char *buffer, char count)
{
char i;
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = addr | CC1101_WRITE_BURST; // Send address
while (!(IFG2&UTXIFG1)); // Wait for TX to finish??
for (i = 0; i < count; i++)
{
U1TXBUF = buffer[i]; // Send data
while (!(IFG2&UTXIFG1)); // Wait for TX to finish??
}
IFG2 &= ~URXIFG1;
while(!(IFG2&URXIFG1));
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
}
char CC1101_SPIReadReg(char addr)
{
char x;
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = (addr | CC1101_READ_SINGLE); // Send address
while (!(IFG2&URXIFG1)); // Wait for TXBUF ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = 0; // Load dummy byte for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of dummy byte TX
x = U1RXBUF; // Read data
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
return x;
}
void CC1101_SPIReadBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = (addr | CC1101_READ_BURST); // Send address
while (!(IFG2&URXIFG1)); // Wait for TXBUF ready
U1TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG2&URXIFG1)); // Wait for end of addr byte TX
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
for (i = 0; i < (count-1); i++)
{
U1TXBUF = 0; //Initiate next data RX, meanwhile..
buffer[i] = U1RXBUF; // Store data from last data RX
while (!(IFG2&URXIFG1)); // Wait for end of data RX
}
buffer[count-1] = U1RXBUF; // Store last RX byte in buffer
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
}
char CC1101_SPIReadStatus(char addr)
{
char x;
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag set during last write
U1TXBUF = (addr | CC1101_READ_BURST); // Send address
while (!(IFG2&URXIFG1)); // Wait for TX to finish
IFG2 &= ~URXIFG1; // Clear flag set during last write
U1TXBUF = 0; // Dummy write so we can read data
while (!(IFG2&URXIFG1)); // Wait for RX to finish
x = U1RXBUF; // Read data
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
return x;
}
void CC1101_SPIStrobe(char strobe)
{
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
}
void CC1101_PowerupReset(void)
{
CC1101_CSn_PxOUT |= CC1101_CSn_PIN;
CC1101_Wait(30);
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN;
CC1101_Wait(30);
CC1101_CSn_PxOUT |= CC1101_CSn_PIN;
CC1101_Wait(45);
CC1101_CSn_PxOUT &= ~CC1101_CSn_PIN; // /CS enable
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = CC1101_SRES; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
while (CC1101_SPI_USART1_PxIN&CC1101_SPI_USART1_SOMI);
CC1101_CSn_PxOUT |= CC1101_CSn_PIN; // /CS disable
}
char CC1101_ReceivePacket(char *rxBuffer, char *length)
{
char status[2];
char pktLen;
// Delayms(1);
if ((CC1101_SPIReadStatus(CC1101_RXBYTES) & CC1101_NUM_RXBYTES))
{
pktLen = CC1101_SPIReadReg(CC1101_RXFIFO); // Read length byte
if (pktLen <= *length) // If pktLen size <= rxBuffer
{
CC1101_SPIReadBurstReg(CC1101_RXFIFO, rxBuffer, pktLen); // Pull data
*length = pktLen; // Return the actual size
CC1101_SPIReadBurstReg(CC1101_RXFIFO, status, 2);//读出校验位
CC1101_SPIStrobe(CC1101_SFRX);
CC1101_SPIStrobe(CC1101_SRX);
// Read appended status bytes
return (char)(status[CC1101_LQI_RX]&CC1101_CRC_OK);//校验成功检验
} // Return CRC_OK bit
else
{
*length = pktLen; // Return the large size
CC1101_SPIStrobe(CC1101_SFRX); // Flush RXFIFO
// CC1101_SPIStrobe(CC1101_SRX);
return 0; // Error
}
}
else
{
CC1101_SPIStrobe(CC1101_SFRX); // Flush RXFIFO
CC1101_SPIStrobe(CC1101_SRX);
return 0; // Error
}
}
void CC1101_SendPacket(char *txBuffer, char size)
{
CC1101_SPIStrobe(CC1101_SIDLE);
CC1101_Wait(10);
CC1101_SPIWriteBurstReg(CC1101_TXFIFO, txBuffer, size); // Write TX data
CC1101_SPIStrobe(CC1101_STX); // Change state to TX, initiating
// data transfer
while (!(CC1101_GDO0_PxIN&CC1101_GDO0_PIN));
// Wait GDO0 to go hi -> sync TX'ed
while (CC1101_GDO0_PxIN&CC1101_GDO0_PIN);
// Wait GDO0 to clear -> end of pkt
CC1101_SPIStrobe(CC1101_SRX);
}
void CC1101_Init(void)
{
CC1101_UART_SPISetup(); // Initialize SPI port
CC1101_PowerupReset(); // Reset CCxxxx
CC1101_Write_Settings(); // Write RF settings to config reg
CC1101_SPIWriteBurstReg(CC1101_PATABLE, paTable, paTableLen);//Write PATABLE
}
char txBuffer[4];
char rxBuffer[4];
void F149_Osc_Init(void)
{
unsigned char i;
BCSCTL1 &= ~XT2OFF; // 打开高速振荡器，使用8M晶振
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag OFIFG：外部晶振故障中断标志
for (i = 0xFF; i > 0; i--); // Time for flag to set
}while ((IFG1 & OFIFG)); // OSCFault flag still set? 振荡电路是否正常
BCSCTL2 |= SELM_2 + SELS ; // MCLK= SMCLK = XT2= (safe)
}
void F149_UART0_Init(void)
{
U0CTL=SWRST+CHAR;
U0TCTL=SSEL0; //ACLK
U0BR0=0X03;
U0BR1=0X00;
U0MCTL=0X4a;
U0CTL &=~SWRST; //SWRST=0
ME1 |=UTXE0+URXE0;
IE1 |=0;
P3SEL |=BIT4+BIT5;
P3DIR |=BIT4;
}
void Delayms(unsigned int delay) //10 MCLK=1.25uS
{
unsigned long v;
for (v=((long)delay*800);v>0;v--);
}
void main (void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
F149_Osc_Init();
F149_UART0_Init();
U0TXBUF=1;
while((UTCTL0&0x01)==0);
CC1101_Init();
U0TXBUF=2;
while((UTCTL0&0x01)==0);
CC1101_GDO0_PxIES |= CC1101_GDO0_PIN; // Int on falling edge 下降沿(end of pkt)
CC1101_GDO0_PxIFG &= ~CC1101_GDO0_PIN; // Clear flag
CC1101_GDO0_PxIE |= CC1101_GDO0_PIN; // Enable int on end of packet
CC1101_SPIStrobe(CC1101_SIDLE); // Initialize CCxxxx in RX mode.
_EINT(); // When a pkt is received, it will
// signal on GDO0 and wake CPU
U0TXBUF=CC1101_SPIReadStatus(CC1101_BSCFG);
while((UTCTL0&0x01)==0);
U0TXBUF=CC1101_SPIReadStatus(CC1101_PATABLE);
while((UTCTL0&0x01)==0);
U0TXBUF=CC1101_SPIReadStatus(CC1101_PKTLEN);
while((UTCTL0&0x01)==0);
U0TXBUF=CC1101_SPIReadStatus(CC1101_CHANNR);
while((UTCTL0&0x01)==0);
U0TXBUF=CC1101_SPIReadStatus(CC1101_ADDR);
while((UTCTL0&0x01)==0);
while(1)
{
Delayms(1000);
txBuffer[0] = 2; // Packet length
txBuffer[1] = 0x01; // Packet address
txBuffer[2] = 0xad;// Load four switch inputs
U0TXBUF=4;
while((UTCTL0&0x01)==0);
// CC1101_SendPacket(txBuffer, 3);// Send value over RF
//CC1101_SPIStrobe(CC1101_SIDLE);
CC1101_SPIWriteReg(0x3F, 3);
CC1101_SPIStrobe(CC1101_STX);
Delayms(1000);
// P1IFG &= ~CC1101_GDO0_PIN;
// CC1101_SPIStrobe(CC1101_SIDLE);
U0TXBUF=3;
while((UTCTL0&0x01)==0);
}
}
/*
// The ISR assumes the interrupt came from a press of one of the four buttons
// and therefore does not check the other four inputs.
#pragma vector=PORT1_VECTOR
__interrupt void port1_ISR (void)
{
// Build packet
txBuffer[0] = 2; // Packet length
txBuffer[1] = 0x01; // Packet address
txBuffer[2] = 0xad;// Load four switch inputs
CC1101_SendPacket(txBuffer, 3); // Send value over RF
P1IFG &= ~CC1101_GDO0_PIN; // After pkt TX, this flag is set.
} // Clear it.
// The ISR assumes the int came from the pin attached to GDO0 and therefore
// does not check the other seven inputs. Interprets this as a signal from
// CCxxxx indicating packet received.
#pragma vector=PORT1_VECTOR
__interrupt void port1_ISR (void)
{
char len=2; // Len of pkt to be RXed (only addr
// plus data; size byte not incl b/c
// stripped away within RX function)
CC1101_ReceivePacket(rxBuffer,&len); // Fetch packet from CCxxxx
U0TXBUF=rxBuffer[1];
while((UTCTL0&0x01)==0);
U0TXBUF=rxBuffer[2];
while((UTCTL0&0x01)==0);
P1IFG &= ~CC1101_GDO0_PIN; // Clear flag
}
*/
void CC1101_Write_Settings(void)
{
// Write register settings
CC1101_SPIWriteReg(CC1101_IOCFG2, 0x0B); // GDO2 output pin config.
CC1101_SPIWriteReg(CC1101_IOCFG0, 0x06); // GDO0 output pin config.
CC1101_SPIWriteReg(CC1101_FIFOTHR, 0x47);
CC1101_SPIWriteReg(CC1101_PKTLEN, 0xFF); // Packet length.
CC1101_SPIWriteReg(CC1101_PKTCTRL1, 0x04); // Packet automation control.
CC1101_SPIWriteReg(CC1101_PKTCTRL0, 0x05); // Packet automation control.
CC1101_SPIWriteReg(CC1101_ADDR, 0x00); // Device address.
CC1101_SPIWriteReg(CC1101_CHANNR, 0x06); // Channel number.
CC1101_SPIWriteReg(CC1101_FSCTRL1, 0x06); // Freq synthesizer control.
CC1101_SPIWriteReg(CC1101_FSCTRL0, 0x00); // Freq synthesizer control.
CC1101_SPIWriteReg(CC1101_FREQ2, 0x23); // Freq control word, high byte
CC1101_SPIWriteReg(CC1101_FREQ1, 0x31); // Freq control word, mid byte.
CC1101_SPIWriteReg(CC1101_FREQ0, 0x3B); // Freq control word, low byte.
CC1101_SPIWriteReg(CC1101_MDMCFG4, 0xF8); // Modem configuration.
CC1101_SPIWriteReg(CC1101_MDMCFG3, 0x83); // Modem configuration.
CC1101_SPIWriteReg(CC1101_MDMCFG2, 0x03); // Modem configuration.
CC1101_SPIWriteReg(CC1101_MDMCFG1, 0x22); // Modem configuration.
CC1101_SPIWriteReg(CC1101_MDMCFG0, 0xF8); // Modem configuration.
CC1101_SPIWriteReg(CC1101_DEVIATN, 0x14); // Modem dev (when FSK mod en)
CC1101_SPIWriteReg(CC1101_MCSM1 , 0x07); //MainRadio Cntrl State Machine
CC1101_SPIWriteReg(CC1101_MCSM0 , 0x18); //MainRadio Cntrl State Machine
CC1101_SPIWriteReg(CC1101_FOCCFG, 0x16); // Freq Offset Compens. Config
CC1101_SPIWriteReg(CC1101_BSCFG, 0x6C); // Bit synchronization config.
CC1101_SPIWriteReg(CC1101_AGCCTRL2, 0x43); // AGC control.
CC1101_SPIWriteReg(CC1101_AGCCTRL1, 0x40); // AGC control.
CC1101_SPIWriteReg(CC1101_AGCCTRL0, 0x91); // AGC control.
CC1101_SPIWriteReg(CC1101_FREND1, 0x56); // Front end RX configuration.
CC1101_SPIWriteReg(CC1101_FREND0, 0x10); // Front end RX configuration.
CC1101_SPIWriteReg(CC1101_FSCAL3, 0xE9); // Frequency synthesizer cal.
CC1101_SPIWriteReg(CC1101_FSCAL2, 0x2A); // Frequency synthesizer cal.
CC1101_SPIWriteReg(CC1101_FSCAL1, 0x00); // Frequency synthesizer cal.
CC1101_SPIWriteReg(CC1101_FSCAL0, 0x1F); // Frequency synthesizer cal.
CC1101_SPIWriteReg(CC1101_FSTEST, 0x59); // Frequency synthesizer cal.
CC1101_SPIWriteReg(CC1101_TEST2, 0x81); // Various test settings.
CC1101_SPIWriteReg(CC1101_TEST1, 0x35); // Various test settings.
CC1101_SPIWriteReg(CC1101_TEST0, 0x09); // Various test settings.
}
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发表于 2012-4-13 14:57:51
