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问题,如题,代码如下:
`define DEBUG 1
module fifo_uart_tx(
CLK,
NRESET,
DATA,
WR,
FULL,
TX
);
parameter IDLE =0,
S =1,
B0 =2,
B1 =3,
B2 =4,
B3 =5,
B4 =6,
B5 =7,
B6 =8,
B7 =9,
E =10;
input CLK;//48Mhz系统时钟频率
input NRESET;
input [7:0]DATA;
input WR;
output FULL;
output TX;
reg[3:0] current_state;
reg[3:0] next_state;
reg [1:0]baud_clk_r;
reg rd_r;
reg tx_r;
reg clk_en_r;
wire clk_en;
wire baud_clk;
wire rd;
wire empty;
wire [7:0]q;
wire pos_baud_clk;
//实例化一个时钟产生模块
baud_gen baud_gen(
.CLK(CLK),
.NRESET(NRESET),
.EN(clk_en),
.BAUD_CLK(baud_clk)
);
//实例化一个 FIFO
fifo fifo_inst (
.aclr ( NRESET ),
.clock ( CLK ),
.data ( DATA ),
.rdreq ( rd ),
.wrreq ( WR ),
.empty ( empty ),
.full ( FULL ),
.q ( q )
);
always@(posedge CLK,negedge NRESET)
if(!NRESET)
baud_clk_r[0]<=0;
else
baud_clk_r[0]<=baud_clk;
always@(posedge CLK,negedge NRESET)
if(!NRESET)
baud_clk_r[1]<=0;
else
baud_clk_r[1]<=baud_clk_r[0];
assign pos_baud_clk=~baud_clk_r[1]&baud_clk_r[0];//baud_clk的上升沿
always@(posedge CLK,negedge NRESET)
if(!NRESET)
current_state<=IDLE;
else
current_state<=next_state;
always@(current_state,pos_baud_clk,empty) begin
case(current_state)
IDLE: if(!empty)
next_state=S;
S: if(pos_baud_clk)
next_state=B0;
B0: if(pos_baud_clk)
next_state=B1;
B1: if(pos_baud_clk)
next_state=B2;
B2: if(pos_baud_clk)
next_state=B3;
B3: if(pos_baud_clk)
next_state=B4;
B4: if(pos_baud_clk)
next_state=B5;
B5: if(pos_baud_clk)
next_state=B6;
B6: if(pos_baud_clk)
next_state=B7;
B7: if(pos_baud_clk)
next_state=E ;
E: if(pos_baud_clk)
next_state=IDLE ;
endcase
end
always@(posedge CLK,negedge NRESET) begin
if(!NRESET) begin
tx_r<=1;
rd_r<=0;
clk_en_r<=0;
end
else
case(next_state)
IDLE:begin
if(!empty)
rd_r<=1;
else
rd_r<=0;
tx_r<=1;
clk_en_r<=0;
end
S:begin
clk_en_r<=1;
tx_r<=0;
rd_r<=0;
end
B0:tx_r<=q[0];
B1:tx_r<=q[1];
B2:tx_r<=q[2];
B3:tx_r<=q[3];
B4:tx_r<=q[4];
B5:tx_r<=q[5];
B6:tx_r<=q[6];
B7:tx_r<=q[7];
E: tx_r<=1;
endcase
end
assign TX=tx_r;
assign clk_en=clk_en_r;
assign rd=rd_r;
endmodule
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阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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