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我最近才开始玩FPGA,用的是nexys3,vhdl也是最近才开始学的。尝试控制板上的psram。程序是我自己写的,前5秒写入,后5秒读出。但是,无论怎么改程序,读出来的都是零。
麻烦大家帮我看一下
时钟是100mhz,那个psram是微芯的MT45W8MW16BGX,就是nexys3上那块。
entity testRAM is port
(
---ram signal
add:out std_logic_vector(22 downto 0);
data:inout std_logic_vector(15 downto 3);
clkram:out std_logic:='0';
adv:out std_logic:='0';
oe:out std_logic:='0';
lb:out std_logic:='0';
hb:out std_logic:='0';
ce:out std_logic:='1';
wr:out std_logic:='1';
---led signal
led:out std_logic_vector(7 downto 0);
clk:in std_logic
);
end testRAM;
architecture Behavioral of testRAM is
signal CLKDIV: STD_LOGIC:='0';
signal re:std_logic:='0';
signal we:std_logic:='0';
signal mydatain,mydataout:std_logic_vector(15 downto 3);
signal myadd:std_logic_vector(22 downto 0);
signal a,b:std_logic:='0';
signal bt:std_logic:='0';
begin
div:process(clk)
variable cn:natural;
begin
if clk='1' and clk'EVENT THEN
CN:=CN+1;
IF CN=50000000 THEN
CLKDIV<=NOT CLKDIV;
CN:=0;
END IF;
END IF;
END process;
ramop:process(clkdiv)
variable c:natural :=0;
begin
if(rising_edge(clkdiv))then
c:=c+1;
if(c>=5)then
c:=0;
bt<=not bt;
end if;
if(bt='0')then
re<='0';
we<='1';
mydatain<= conv_std_logic_vector(c,13);
myadd<= conv_std_logic_vector(1024+c,23);
else
myadd<=conv_std_logic_vector(1024+c,23);
re<='1';
we<='0';
end if;
end if;
end process;
process(clk,we)
variable c:natural:=0;
begin
if(rising_edge(clk) and we='1')then
c:=c+1;
case c is
when 1 =>
data<=mydatain;
wr<='0';
when 8 =>
wr<='1';
c:=0;
we<='0';
when others =>
null;
end case;
end if;
end process;
process(clk,re)
variable c:natural:=0;
begin
if(rising_edge(clk) and re='1')then
c:=c+1;
case c is
when 1 =>
null;
when 8=>
mydataout<=data;
re<='0';
c:=0;
when others =>
null;
end case;
end if;
end process;
led<=mydatain(10 downto 3) when we='1'
else not mydataout(10 downto 3) when re='1'
else "00000000";
add<=myadd;
ce<='0';
end Behavioral;
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阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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