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module top(led_dat,bus_ale,bus_wr,bus_add_l,bus_rd,bus_add_h,led_seg);
output[7:0] led_dat; //测试LED
reg[7:0] led_dat;
output[7:0] led_seg; //测试LED段位
reg[7:0] led_seg;
input bus_ale; //总线操作
input bus_wr; //总线写
input bus_rd; //总线读
input[7:0] bus_add_h; //总线地址高8位
reg[15:0] bus_add; //16位地址总线
inout[7:0] bus_add_l; //总线低8位 & 数据
reg bus_dat_oe=0; //bus_add_l输出使能 默认禁止输出
reg[7:0] bus_dat_out; //bus_add_l输出缓存
reg[7:0] bus_dat_in; //bus_add_l输入缓存
assign bus_add_l=bus_dat_oe?bus_dat_out:8'hz; //如果输出使能 则输出,否则高阻
always @(negedge bus_ale) //获取总线地址
begin
bus_add={bus_add_h[7:0],bus_add_l[7:0]};
end
always @(negedge bus_wr) //总线写操作 读取数据
begin
bus_dat_in=bus_add_l;
case (bus_add)
16'h1:led_seg=bus_dat_in;
16'h2:led_dat=bus_dat_in;
endcase
end
always @(negedge bus_rd) //总线读操作 输出数据
begin
case (bus_add)
16'h1000:bus_dat_out=8'h01;
16'h00f1:bus_dat_out=8'hf2;
default:bus_dat_out=8'hx;
endcase
bus_dat_oe=1'b1;
end
always @(posedge bus_rd) //总线读操作复位
begin
bus_dat_oe=1'b0; //error1
end
endmodule
//error1 总是在此处提示错误~
Error (10028): Can't resolve multiple constant drivers for net "bus_dat_oe" at top.v(45)
Error (10029): Constant driver at top.v(35)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 169 megabytes
Error: Processing ended: Wed Feb 08 10:12:59 2012
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings
还请大家指点,另外inout数据类型是这样用的么?我这是与51单片机构成总线~
之前51单片机写总线没有问题了,可读的时候我改成了双向IO口,但这样编译出错~ |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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