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发表于 2015-1-25 22:12:47
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显示全部楼层
这是我现在用的PWM,交流一下。使用FPGA实现的。
- module pwm(clk,pwm0,pwm1,pwm2,pwm3,in_pwm_0,in_pwm_1,in_pwm_2,in_pwm_3,rst);
- input clk; //50MHz时钟信号
- input rst;
- input [7:0] in_pwm_0,in_pwm_1,in_pwm_2,in_pwm_3; //PWM控制波输入
- output reg pwm0,pwm1,pwm2,pwm3; //PWM波输出
- reg[16:0] cnt,cnt50; //计时变量
- reg[16:0] clk_50;
- always @(posedge clk or negedge rst)
- begin
- //---------------计数器计数-----------------------------
- if (!rst)
- begin
- cnt=0;
- end
- else if(cnt=='d999)
- begin
- cnt<='b00000;
- clk_50=1;
- end
- else
- begin
- cnt<=cnt+1;
- clk_50=0;
- end
- end
- //--------------pwm的产生---------------
- always @(posedge clk_50 or negedge rst)
- begin
- if (!rst)
- begin
- pwm0=0;
- pwm1=0;
- pwm2=0;
- pwm3=0;
- end
- else
- begin
- if (cnt50==999) cnt50=0; else cnt50=cnt50+1;
- if (cnt50<in_pwm_0) pwm0=1; else pwm0=0;
- if (cnt50<in_pwm_1) pwm1=1; else pwm1=0;
- if (cnt50<in_pwm_2) pwm2=1; else pwm2=0;
- if (cnt50<in_pwm_3) pwm3=1; else pwm3=0;
- end
- end
- endmodule
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