那位仁兄做过中值滤波的Verilog实现啊

haixiaowujun

求一个

zkf0100007

自己编一个也不是很难吧

zkf0100007

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity filter_test is
        Port (img_d0 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d1 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d2 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d3 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d4 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d5 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d6 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d7 : in  STD_LOGIC_VECTOR (7 downto 0);
              img_d8 : in  STD_LOGIC_VECTOR (7 downto 0);
                  
              img_out : out  STD_LOGIC_VECTOR (7 downto 0));
end filter_test;

architecture Behavioral of filter_test is

signal g1_out : STD_LOGIC_VECTOR (7 downto 0);
signal g2_out : STD_LOGIC_VECTOR (7 downto 0);
signal g3_out : STD_LOGIC_VECTOR (7 downto 0);
signal g4_out : STD_LOGIC_VECTOR (7 downto 0);
signal g5_out : STD_LOGIC_VECTOR (7 downto 0);
signal g6_out : STD_LOGIC_VECTOR (7 downto 0);
signal g7_out : STD_LOGIC_VECTOR (7 downto 0);

signal g8_out : STD_LOGIC_VECTOR (7 downto 0);
signal g9_out : STD_LOGIC_VECTOR (7 downto 0);
signal g10_out : STD_LOGIC_VECTOR (7 downto 0);
signal g11_out : STD_LOGIC_VECTOR (7 downto 0);
signal g12_out : STD_LOGIC_VECTOR (7 downto 0);
signal g13_out : STD_LOGIC_VECTOR (7 downto 0);
signal g14_out : STD_LOGIC_VECTOR (7 downto 0);

signal g15_out : STD_LOGIC_VECTOR (7 downto 0);
signal g16_out : STD_LOGIC_VECTOR (7 downto 0);
signal g17_out : STD_LOGIC_VECTOR (7 downto 0);

signal g18_out : STD_LOGIC_VECTOR (7 downto 0);
signal g19_out : STD_LOGIC_VECTOR (7 downto 0);

signal g1_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g2_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g3_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g4_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g5_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g6_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g7_out1 : STD_LOGIC_VECTOR (7 downto 0);

signal g8_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g9_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g10_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g11_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g12_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g13_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g14_out1 : STD_LOGIC_VECTOR (7 downto 0);

signal g15_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g16_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g17_out1 : STD_LOGIC_VECTOR (7 downto 0);

signal g18_out1 : STD_LOGIC_VECTOR (7 downto 0);
signal g19_out1 : STD_LOGIC_VECTOR (7 downto 0);

signal g1_func : STD_LOGIC_VECTOR (7 downto 0);
signal g2_func : STD_LOGIC_VECTOR (7 downto 0);
signal g3_func : STD_LOGIC_VECTOR (7 downto 0);
signal g4_func : STD_LOGIC_VECTOR (7 downto 0);
signal g5_func : STD_LOGIC_VECTOR (7 downto 0);
signal g6_func : STD_LOGIC_VECTOR (7 downto 0);
signal g7_func : STD_LOGIC_VECTOR (7 downto 0);

signal g8_func : STD_LOGIC_VECTOR (7 downto 0);
signal g9_func : STD_LOGIC_VECTOR (7 downto 0);
signal g10_func : STD_LOGIC_VECTOR (7 downto 0);
signal g11_func : STD_LOGIC_VECTOR (7 downto 0);
signal g12_func : STD_LOGIC_VECTOR (7 downto 0);
signal g13_func : STD_LOGIC_VECTOR (7 downto 0);
signal g14_func : STD_LOGIC_VECTOR (7 downto 0);

signal g15_func : STD_LOGIC_VECTOR (7 downto 0);
signal g16_func : STD_LOGIC_VECTOR (7 downto 0);
signal g17_func : STD_LOGIC_VECTOR (7 downto 0);

signal g18_func : STD_LOGIC_VECTOR (7 downto 0);
signal g19_func : STD_LOGIC_VECTOR (7 downto 0);

begin

g1_out<=img_d8 when img_d8>img_d7 else
        img_d7;       
g1_out1<=img_d8 when img_d8<img_d7 else
         img_d7;

g2_out<=img_d5 when img_d5>img_d4 else
        img_d4;       
g2_out1<=img_d5 when img_d5<img_d4 else
         img_d4;
                       
g3_out<=img_d2 when img_d2>img_d1 else
        img_d1;       
g3_out1<=img_d2 when img_d2<img_d1 else
         img_d1;
                       
g4_out<=g1_out1 when g1_out1>img_d6 else
        img_d6;       
g4_out1<=g1_out1 when g1_out1<img_d6 else
         img_d6;       

g5_out<=g2_out1 when g2_out1>img_d3 else
        img_d3;       
g5_out1<=g2_out1 when g2_out1<img_d3 else
         img_d3;
                       
g6_out<=g3_out1 when g3_out1>img_d0 else
        img_d0;       
g6_out1<=g3_out1 when g3_out1<img_d0 else
         img_d0;

g7_out<=g1_out when g1_out>g4_out else
        g4_out;       
g7_out1<=g1_out when g1_out<g4_out else
         g4_out;

g8_out<=g2_out when g2_out>g5_out else
        g5_out;       
g8_out1<=g2_out when g2_out<g5_out else
         g5_out;

g9_out<=g3_out when g3_out>g6_out else
        g6_out;       
g9_out1<=g3_out when g3_out<g6_out else
         g6_out;       

g10_out<=g7_out when g7_out>g8_out else
         g8_out;       
g10_out1<=g7_out when g7_out<g8_out else
          g8_out;

g11_out<=g10_out1 when g10_out1>g9_out else
         g9_out;       
g11_out1<=g10_out1 when g10_out1<g9_out else
          g9_out;

g12_out<=g7_out1 when g7_out1>g8_out1 else
         g8_out1;       
g12_out1<=g7_out1 when g7_out1<g8_out1 else
          g8_out1;

g13_out<=g5_out1 when g5_out1>g6_out1 else
         g6_out1;       
g13_out1<=g5_out1 when g5_out1<g6_out1 else
          g6_out1;

g14_out<=g12_out1 when g12_out1>g9_out1 else
         g9_out1;       
g14_out1<=g12_out1 when g12_out1<g9_out1 else
          g9_out1;

g15_out<=g4_out1 when g4_out1>g13_out else
         g13_out;       
g15_out1<=g4_out1 when g4_out1<g13_out else
          g13_out;

g16_out<=g12_out when g12_out>g14_out else
         g14_out;       
g16_out1<=g12_out when g12_out<g14_out else
          g14_out;

g17_out<=g11_out1 when g11_out1>g16_out1 else
         g16_out1;       
g17_out1<=g11_out1 when g11_out1<g16_out1 else
          g16_out1;

g18_out<=g17_out1 when g17_out1>g15_out else
         g15_out;       
g18_out1<=g17_out1 when g17_out1<g15_out else
          g15_out;       

g19_out<=g17_out when g17_out>g18_out else
         g18_out;       
g19_out1<=g17_out when g17_out<g18_out else
          g18_out;

img_out<=g19_out1;       

                       
end Behavioral;

archi9966

zkf0100007 发表于 2011-12-15 16:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

很赞啊！！

zkf0100007

archi9966 发表于 2013-10-25 23:24
很赞啊！！

这个是纯组合逻辑的，如果工作频率较高，可考虑在没一级加入寄存器

archi9966

zkf0100007 发表于 2013-10-26 11:25
这个是纯组合逻辑的，如果工作频率较高，可考虑在没一级加入寄存器

嗯，好的谢谢啦

蓝色风暴@FPGA

这个应该比较好实现、一直比较下去就好了