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楼主 |
发表于 2011-12-14 09:04:40
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module Q_switch(CLK,Pwm);
parameter Pulse_width=16'd10;
parameter Cycle_pwm=16'd50;
input CLK;
output Pwm;
reg[23:0] CNT;
reg[15:0] pwm_cnt1,pwm_cnt2;
reg Pwm,pwm_status;
always@(posedge CLK)
begin
CNT=CNT+24'd1;
if(CNT==24'd10)//ns计数
begin
CNT=24'd0000000;
if(pwm_cnt1<Pulse_width)
begin
pwm_status=1'd1;
Pwm = pwm_status;//高电平
end
else
begin
pwm_status=1'd0;
Pwm = pwm_status;//低电平
end
pwm_cnt1=pwm_cnt1+16'd1;
if(pwm_cnt1>=Cycle_pwm)
begin
pwm_cnt1=pwm_cnt1+16'd0;
end
end
end
endmodule
这是写的,刚开始学,还请多指教啊!分频出来的也是15HZ左右的波形 |
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