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发表于 2011-12-9 19:19:28
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Sitara AM335x
Device Summary
1.1 Features
• Highlights – 256KB of L2 Cache with Error Correcting
– 500-MHz, 600-MHz, or 720-MHz ARM® Code (ECC)
Cortex™-A8 32-Bit RISC Microprocessor – 176KB of On-Chip Boot ROM
• NEON™ SIMD Coprocessor – 64KB of Dedicated RAM
• 32KB/32KB of L1 Instruction/Data Cache – Emulation/Debug
with Single-Error Detection (parity) • JTAG
• 256KB of L2 Cache with Error Correcting • Embedded Trace Module
Code (ECC) • Embedded Trace Buffer
– mDDR(LPDDR)/DDR2/DDR3 Support – Interrupt Controller (up to 128 interrupt
– General-Purpose Memory Support (NAND, requests)
NOR, SRAM, etc.) Supporting Up to 16-bit • On-Chip Memory (Shared L3 RAM)
ECC – 64 KB of General-Purpose On-Chip Memory
– SGX530 Graphics Engine Controller (OCMC) RAM
– Programmable Real-Time Unit Subsystem – Accessible to all Masters
– Real-Time Clock (RTC) – Supports Retention for Fast Wake-Up
– Up to Two USB 2.0 High-Speed OTG Ports • External Memory Interfaces (EMIF)
with Integrated PHY – mDDR/DDR2/DDR3 Controller:
– 10/100/1000 Ethernet Switch Supporting Up • mDDR: 200-MHz Clock (400-MHz Data
to Two Ports Rate)
– Two Controller Area Network Ports (CAN) • DDR2: 266-MHz Clock (532-MHz Data
– Six UARTs, Two McASPs, Two McSPI, and Rate)
Two I2C Ports • DDR3: 303-MHz Clock (606-MHz Data
– 12-Bit Successive Approximation Register Rate)
(SAR) ADC • 16-Bit Data Bus
– Up to Three 32-Bit Enhanced Capture • 1 GB of Total Addressable Space
Modules (eCAP) • Supports One x16, Two x8, or Four x4
– Up to Three Enhanced High-Resolution PWM Memory Device Configurations
Modules (eHRPWM) • Supports Retention for Fast Wake-Up
– Crypto Hardware Accelerators (AES, SHA, – General-Purpose Memory Controller (GPMC) PKA, RNG)
• Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
• MPU Subsystem (NAND, NOR, Muxed-NOR, SRAM, etc.)
– 500-MHz, 600-MHz, or 720-MHz ARM® • Uses BCH Code to Support 4-Bit, 8-Bit, or
Cortex™-A8 32-Bit RISC Microprocessor 16-Bit ECC
– NEON™ SIMD Coprocessor • Uses Hamming Code to Support 1-Bit
– 32KB of L1 Instruction Cache with ECC
Single-Error Detection (parity) – Error Locator Module (ELM)
– 32KB of L1 Data Cache with Single • Used in Conjunction with the GPMC to
Error-Detection (parity) Locate Addresses of Data Errors from |
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发表于 2011-12-9 18:33:34
