SmartFusion FPGA带硬的主流ARM® Cortex™-M3，可以充分利用现有STM

Fusionics

icrocontroller Subsystem (MSS)
• Hard 100 MHz 32-Bit ARM® Cortex™-M3
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
• Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
• Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,1 Allowing Multi-Master Schemes
• 10/100 Ethernet MAC with RMII Interface2
• Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
• Two I2C Peripherals
• Two 16550 Compatible UARTs
• Two SPI Peripherals
• Two 32-Bit Timers
• 32-Bit Watchdog Timer
• 8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
• Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)