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module MENC_Div(
in1_A,in1_B,
rst_n,
out_A,out_B
);
input in1_A;
input in1_B;
input rst_n;
output out_A;
output out_B;
reg [1:0] oldAB;
reg [1:0] status;
reg [3:0] cnt;
reg out_A_reg,out_B_reg;
//用于对in1_A、in1_B下降沿敏感
wire in2_A=~in1_A;
wire in2_B=~in1_B;
wire [1:0] AB={in1_A,in1_B};
//输入A、B辩向,生成状态数据status
always @ ( posedge in1_A or posedge in2_A or
posedge in1_B or posedge in2_B or
negedge rst_n)
begin
if(!rst_n)
begin
//AB=2'b00;
oldAB=AB;
status=2'b00;
end
else
begin //编码器增量信号解码
//AB={in1_A,in1_B};
case (AB)
2'b00 :
case (oldAB)
2'b01 : status=2'b01; //2'b01-正转
2'b10 : status=2'b10; //2'b10-反转
default :status=2'b11; //2'b00、2'b11-错误信号
endcase
2'b01 :
case (oldAB)
2'b00 : status=2'b10; //反转
2'b11 : status=2'b01; //正转
default :status=2'b11;
endcase
2'b10 :
case (oldAB)
2'b00 : status=2'b01; //正转
2'b11 : status=2'b10; //反转
default :status=2'b11;
endcase
2'b11 :
case (oldAB)
2'b01 : status=2'b10; //反转
2'b10 : status=2'b01; //正转
default :status=2'b11;
endcase
//default :;
endcase
oldAB<=AB;//不能用阻塞
end
end
//循环的对A、B的沿计数,1-15,生成counter
always @ ( posedge in1_A or //posedge in2_A or
//posedge in1_B or //posedge in2_B or
negedge rst_n
)//两个敏感时可以编译、综合,但也不对
//三个敏感时,报错
begin
if(!rst_n)
cnt<=1'b1;
else
if(status==2'b01) //2'b01-正转
if(cnt==4'd15)cnt<=1'b1;
else cnt<=cnt+1'b1;
else
if(status==2'b10) //2'b10-反转
if(cnt==4'd15)cnt<=4'd15;
else cnt<=cnt-1'b1;
else cnt<=1'b1; //2'b00、2'b11-错误信号
end
assign out_A=out_A_reg;
assign out_B=out_B_reg;
/*
always @ (negedge rst_n)
begin
if(!rst_n)
begin
out_A_reg=in2_A;//{out_A_reg,out_B_reg}=2'b00;
out_B_reg=in2_B;
end
end*/
//生成输出A1、B1 组合逻辑
always @ ( cnt or rst_n)
begin
if(!rst_n)
begin
out_A_reg<=1'b0;//{out_A_reg,out_B_reg}=2'b00;
out_B_reg<=1'b0;
end
else
if(cnt<=4'd4)
begin
out_A_reg<=1'b0; //{out_A_reg,out_B_reg}=2'b00; //任意构建一个正交周期波形
out_B_reg<=1'b0;
end
else
if(cnt<=4'd7) //{out_A_reg,out_B_reg}=2'b10;
begin
out_A_reg<=1'b1;
out_B_reg<=1'b0;
end
else
if(cnt<=4'd11) //{out_A_reg,out_B_reg}=2'b11;
begin
out_A_reg<=1'b1;
out_B_reg<=1'b1;
end
else
if(cnt<=4'd15) //{out_A_reg,out_B_reg}=2'b01;
begin
out_A_reg<=1'b0;
out_B_reg<=1'b1;
end
else
begin
out_A_reg<=1'bx; //不关心,该情况不可能出现
out_B_reg<=1'bx;
end
end
endmodule
报警如下:
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "out_A" is stuck at GND
Warning (13410): Pin "out_B" is stuck at GND
Warning: Design contains 3 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "rst_n"
Warning (15610): No output dependent on input pin "in1_A"
Warning (15610): No output dependent on input pin "in1_B"
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin out_A has GND driving its datain port
Info: Pin out_B has GND driving its datain port
Warning: No paths found for timing analysis |
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