数码管动态扫描的问题

jeasen

如下程序没有问题，显示12345678
---------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan8led is
port(clk:in std_logic;
     led_adder:out std_logic_vector(7 downto 0);
     seg7_data:out std_logic_vector(6 downto 0));
end entity;
architecture wen of scan8led is
signal data_temp:std_logic_vector(7 downto 0):="11111110";
signal clk1:std_logic;
begin
  process(clk)
  variable Q:std_logic_vector(16 downto 0);
  begin
    if clk'event and clk='1' then
      if(Q="11000011010100000") then
           Q:="00000000000000000";
      else Q:=Q+1;
      end if;
     end if;
       clk1<=Q(16);
   end process;
  process(clk1,data_contral)is
  variable c: integer range 1 to 8 :=1;
  begin
    if(clk1'event and clk1='1')then
      led_adder<=data_temp;
      data_temp<=data_temp(6 downto 0)&data_temp(7);
      case c is
        when 1=>seg7_data<="1111001";
        when 2=>seg7_data<="0100100";
        when 3=>seg7_data<="0110000";
        when 4=>seg7_data<="0011001";
        when 5=>seg7_data<="0010010";
        when 6=>seg7_data<="0000010";
        when 7=>seg7_data<="1111000";
        when 8=>seg7_data<="0000000";
      end case;
      c:=c+1;
      if(c=9)then
        c:=1;
      end if;
    end if;
  end process;
end architecture wen;
-----------------------------------------
但做如下修改后本想显示三位动态扫描，结果位码就乱了，数码不能在固定的位显示，三个位轮流跑，而且会出现一个没有设置过的码夹杂在中间，请高手看看怎么回事情？
-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan3led is
port(clk:in std_logic;
     led_adder:out std_logic_vector(2 downto 0);
     seg7_data:out std_logic_vector(6 downto 0));
end entity;
architecture wen of scan3led is
signal data_temp:std_logic_vector(2 downto 0):="110";
signal clk1:std_logic;
begin
  process(clk)
  variable Q:std_logic_vector(16 downto 0);
  begin
    if clk'event and clk='1' then
      if(Q="11000011010100000") then
           Q:="00000000000000000";
      else Q:=Q+1;
      end if;
     end if;
       clk1<=Q(16);
   end process;
  process(clk1,data_contral)is
  variable c: integer range 1 to 3 :=1;
  begin
    if(clk1'event and clk1='1')then
      led_adder<=data_temp;
      data_temp<=data_temp(1 downto 0)&data_temp(2);
      case c is
        when 1=>seg7_data<="1111001";
        when 2=>seg7_data<="0100100";
        when 3=>seg7_data<="0110000";
      end case;
      c:=c+1;
      if(c=4)then
        c:=1;
      end if;
    end if;
  end process;
end architecture wen;

zkf0100007

话说 ,没有谁会愿意帮你分析这一大段代码的 , VHDL这东西 ,最好是插个核用 chipscope看看波形 ,很快就找到问题了 ,另外 ,一般不要用变量 ,推荐用信号

jeasen

大侠，怎么插个核？chipscope是什么？本人新手请赐教！

zkf0100007

Chipscope是 Xilinx的片内逻辑分析工具 ,找本书看看吧 ,如果你用的是 Altera ,也有类似的工具

daicp

先送数据，再打开显示的位