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发表于 2011-8-4 22:20:36
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显示全部楼层
楼上太不负责任了。。。载体就是FPGA了，我有用Verilog做，当然要外接AD和信号调理电路的，只显示波形的话好办，可以VGA硬件画，要是还要控制放大倍数，可选择触发，测量，自动，显示信息什么的就最好嵌核了。其他楼下补充
给你个顶层模块参考下，Verilog做的
////////////////////////////////////top moudle main_ctrl.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SDU
// Engineer: Ljt
// Create Date: 20:08:59 08/28/2010
// Module Name: top_moudule
// Project Name: MPU_VGA
//////////////////////////////////////////////////////////////////////////////////
module vga_top_moudule(
clk,
//VGA的IO
h_sync,v_sync,red,green,blue,
//MicroBlaze核用IO
fpga_0_Micron_RAM_Mem_A_pin,fpga_0_Micron_RAM_Mem_CEN_pin,,fpga_0_Micron_RAM_Mem_OEN_pin,
fpga_0_Micron_RAM_Mem_WEN_pin,fpga_0_Micron_RAM_Mem_BEN_pin,fpga_0_Micron_RAM_Mem_DQ_pin,
fpga_0_rst_1_sys_rst_pin,
//外设
fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin,
fpga_0_Switches_8Bit_GPIO_IO_I_pin,
fpga_0_RS232_PORT_RX_pin,
fpga_0_RS232_PORT_TX_pin,
//键盘
ps2k_clk,ps2k_data,
//AD
max1242_sclk,max1241_cs,max1241_data,sam_clk_out,ad_data,
//EEP//继电器
gpio_5,JiDaQ,
//数字输入，数字输出
digt_in,digt_a,digt_b
);
input clk;//50MHz
//VGA
output h_sync,v_sync;
output [2:0]red;
output [2:0]green;
output [2:0]blue;
//数字输出
output digt_a;
output reg digt_b;
//AD
output max1242_sclk,max1241_cs;
input max1241_data;
//EEP
inout [1:0]gpio_5;
//键盘
input ps2k_clk;
input ps2k_data;
//IP外设
output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_O_pin;
input [7:0] fpga_0_Switches_8Bit_GPIO_IO_I_pin;
input [3:0] fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin;
input fpga_0_RS232_PORT_RX_pin;
output fpga_0_RS232_PORT_TX_pin;
output [3:0] JiDaQ;
input [1:0] digt_in;
//CPU的RAM引脚
output [31:13]fpga_0_Micron_RAM_Mem_A_pin;
output fpga_0_Micron_RAM_Mem_CEN_pin;
output fpga_0_Micron_RAM_Mem_OEN_pin;
output fpga_0_Micron_RAM_Mem_WEN_pin;
output [1:0]fpga_0_Micron_RAM_Mem_BEN_pin;
inout [15:0]fpga_0_Micron_RAM_Mem_DQ_pin;
input fpga_0_rst_1_sys_rst_pin;
//模块之间的互联信号
wire clkb;
wire [11:0] addrb;
wire [31:0] doutb;
wire [12 : 0] addra;
wire [31 : 0] dina;
wire mainclk;
wire clk100M;
wire wea=1;
wire keyclr=1;
wire [31:0]xps_gpio_2_GPIO_IO_I_pin;
wire [31:0]xps_gpio_3_GPIO_IO_I_pin;
wire rst_n=fpga_0_rst_1_sys_rst_pin;
wire [7:0]ps2_byte;
wire ps2_state;
wire [31:0] gpio4;
wire [29:0] iobuf;
wire [23:0] b_doutb;
wire [8:0]markline;
//寄存器变量
//连续性赋值
assign clka=clk100M;
assign xps_gpio_2_GPIO_IO_I_pin[8]=ps2_state;
assign xps_gpio_2_GPIO_IO_I_pin[7:0]=ps2_byte[7:0];
assign xps_gpio_2_GPIO_IO_I_pin[31:9]=0;
assign iobuf=gpio4[31:27];//6位
assign markline=gpio4[10:2];
//assign xps_gpio_3_GPIO_IO_I_pin[16]=max1241_data;//接到了gpio3上
assign max1241_cs=gpio4[1];
assign max1242_sclk=gpio4[0];
wire sam_start,sam_done;
wire [10:0] ad_addra;
//AD IO
output sam_clk_out;
input [9:0]ad_data;
wire sam_clk;
wire [11:0] ad_doutb;//MCU,in
wire [10:0]ad_addrb;//MCU use,o
wire [2:0] clkdivid;//MCU ,o
assign ad_addrb[10:0]=gpio4[21:11];
assign sam_start=gpio4[22];
assign clkdivid[2:0]=gpio4[25:23];
assign xps_gpio_3_GPIO_IO_I_pin[11:0]=ad_doutb[11:0];
assign xps_gpio_3_GPIO_IO_I_pin[22:12]=ad_addra[10:0];
wire trig_1sa;//CPU给出，置1单次触发状态
wire trig_now;//Comp模块给出
assign trig_1sa=gpio4[26];//6位
////////////////////////////////////////////////////例化各个模块
wire [8:0]addrb_b;
wire b_wave_clk;
vga vgadrv (
.mainclk(mainclk),
.h_sync(h_sync),
.v_sync(v_sync),
.red(red),
.green(green),
.blue(blue),
.clkb(clkb),
.addrb(addrb),
.doutb(doutb),
.b_doutb(b_doutb),
.markline(markline),
.addrb_b(addrb_b),
.clk(b_wave_clk)
);
reg [11:0]r_addra; reg [8:0]b_addra;
reg [31:0]r_dina; reg [23:0]b_dina;
b_GRam_wave b_GRam_wave (
.clka(clka),
.wea(wea), // Bus [0 : 0]
.addra(b_addra), // Bus [8 : 0]
.dina(b_dina), // Bus [7 : 0]
.clkb(b_wave_clk),
.addrb(addrb_b), // Bus [8 : 0]
.doutb(b_doutb)); // Bus [7 : 0]
GRam GRam (
.clka(clka),
.wea(wea),
.addra(r_addra),
.dina(r_dina),
.clkb(clkb),
.addrb(addrb),
.doutb(doutb)
);
always@(posedge clk100M)
begin
if(addra[12]) begin b_addra<=addra[8:0]; b_dina<=dina[23:0]; end
else begin r_addra<=addra[11:0]; r_dina<=dina; end
end
wire [3:0]gpio6;
reg [31:0]per_reg;
MicroBlaze MicroBlaze (
.fpga_0_LEDs_8Bit_GPIO_IO_O_pin(fpga_0_LEDs_8Bit_GPIO_IO_O_pin),
.fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin(fpga_0_Push_Buttons_4Bit_GPIO_IO_I_pin),
.fpga_0_Switches_8Bit_GPIO_IO_I_pin(fpga_0_Switches_8Bit_GPIO_IO_I_pin),
.fpga_0_RS232_PORT_RX_pin(fpga_0_RS232_PORT_RX_pin),
.fpga_0_RS232_PORT_TX_pin(fpga_0_RS232_PORT_TX_pin),
.fpga_0_Micron_RAM_Mem_A_pin(fpga_0_Micron_RAM_Mem_A_pin),
.fpga_0_Micron_RAM_Mem_CEN_pin(fpga_0_Micron_RAM_Mem_CEN_pin),
.fpga_0_Micron_RAM_Mem_OEN_pin(fpga_0_Micron_RAM_Mem_OEN_pin),
.fpga_0_Micron_RAM_Mem_WEN_pin(fpga_0_Micron_RAM_Mem_WEN_pin),
.fpga_0_Micron_RAM_Mem_BEN_pin(fpga_0_Micron_RAM_Mem_BEN_pin),
.fpga_0_Micron_RAM_Mem_DQ_pin(fpga_0_Micron_RAM_Mem_DQ_pin),
.fpga_0_clk_1_sys_clk_pin(clk100M),
.fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin),
.xps_gpio_0_GPIO_IO_O_pin(dina),
.xps_gpio_1_GPIO_IO_O_pin(addra),
.xps_gpio_2_GPIO_IO_I_pin(xps_gpio_2_GPIO_IO_I_pin),
.xps_gpio_3_GPIO_IO_I_pin(xps_gpio_3_GPIO_IO_I_pin),
.xps_gpio_4_GPIO_IO_O_pin(gpio4),
.xps_gpio_5_GPIO_IO(gpio_5),
.JiDaQ_GPIO_IO_O_pin(JiDaQ),
.xps_gpio_digt_ctrl_GPIO_IO_O_pin(gpio6),
.xps_gpio_freq_GPIO_IO_I_pin(per_reg)
);
MCU_OutputCantain McuIObuf (
.ioblock(iobuf),
.mainclk(mainclk)
);
ClockManger DPLL (
.CLKIN_IN(clk),
.CLKIN_IBUFG_OUT(CLK0_OUT),
.CLK0_OUT(mainclk),
.CLK2X_OUT(clk100M)
);
ps2scan ps2scan( .clk(mainclk), //按键扫描模块
.rst_n(rst_n),
.ps2k_clk(ps2k_clk),
.ps2k_data(ps2k_data),
.ps2_byte(ps2_byte),
.ps2_state(ps2_state)
);
wire [11:0]ad_data_10bit;
reg [11:0] ad_data_reg;
always@(posedge sam_clk)
ad_data_reg<=ad_data_10bit;
assign ad_data_10bit[11:2]=ad_data[9:0];
assign ad_data_10bit[1:0]=digt_in[1:0];
AD_Cache AD_Cache (
.clka(sam_clk),
.wea(wea), // 1
.addra(ad_addra), //
.dina(ad_data_reg), //ad输入
.clkb(clk100M),
.addrb(ad_addrb), // Bus [10 : 0]
.doutb(ad_doutb)); // Bus [7 : 0]
AD_Sample_Ctrl Sample_Ctrl (
.clk100M(clk100M),
.sam_startin(sam_start),
.clkdivid(clkdivid),
.sam_clk(sam_clk),
.ad_addra(ad_addra),
.trig_now(trig_now),
.sam_clk_out(sam_clk_out)
);
Comp_trig Comp_trig (
.sam_clk(sam_clk),
.clk100M(clk100M),
.trig_1sa(trig_1sa),
.trig_now(trig_now),
.ad_data_reg(ad_data_reg)
);
reg digt_a0;
reg [31:0]per_cnt;
reg digt_freq;
reg digt_a;
reg [15:0] data_cnt;
reg [15:0] c_data_cnt;
always@(posedge clk100M)//频率设置
begin
case(gpio6)
4'h1:data_cnt=16'd500; //100K
4'h2:data_cnt=16'd250; //200K
4'h3:data_cnt=16'd167; //300K 500/3
4'h4:data_cnt=16'd125; //400K 500/4
4'h5:data_cnt=16'd100; //500K
4'h6:data_cnt=16'd83; //600K
4'h7:data_cnt=16'd71; //700K
4'h8:data_cnt=16'd63; //800K
4'h9:data_cnt=16'd56; //900K
4'h10:data_cnt=16'd50; //1M
default:data_cnt=16'd100; //100K
endcase
if(c_data_cnt==data_cnt)
begin
c_data_cnt<=1;
digt_freq<=~digt_freq;
end
else
c_data_cnt<=c_data_cnt+1;
end
always@(posedge clk100M)//频率设置
begin
if(gpio6==0)
digt_a<=ad_data>480;
else
digt_a<=digt_freq;
end
always @(posedge clk100M)
begin
digt_a0<=digt_a;
end
always @(posedge clk100M)
begin
if(digt_a==1&digt_a0==0)//检测到digta上升
begin
per_reg<=per_cnt;//记录周期
per_cnt<=0;
end
else
per_cnt<=per_cnt+1;
end
always @(posedge clk100M)
begin
if(per_cnt>per_reg/8&&per_cnt<per_reg/8+per_reg/8+per_reg/8)//在1/8到3/8周期之间，b为1
digt_b<=1;
else
digt_b<=0;
end
endmodule |
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