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楼主 |
发表于 2011-7-30 14:27:52
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三.下降沿单稳态电路,或类似定时器之类。
clk: 时钟
tclk: 触发输入
delayout :输出脉宽=delaymax*clk周期
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY DELAY_T IS
GENERIC (delaymax:integer:=4);
PORT (
clk : in std_logic;
tclk : in std_logic;
delayout :buffer std_logic);
END DELAY_T;
ARCHITECTURE epm570 OF DELAY_T IS
SIGNAL tclk_1 : std_logic;
BEGIN
PROCESS(tclk,tclk_1)
BEGIN
if (tclk_1='1')then
delayout<='0';
elsif(tclk'EVENT AND tclk = '0')then
delayout<='1';
end if;
END PROCESS;
PROCESS(clk,delayout)
variable delayT: integer range 0 to delaymax:=0;
BEGIN
if (delayout='0')then
delayT:=0;
tclk_1<='0';
else if(clk'EVENT AND clk = '1')then
if(delayT=delaymax)then
tclk_1<='1';
end if;
delayT:=delayT+1;
end if;
end if;
END PROCESS;
END epm570; |
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