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发表于 2011-7-28 02:07:26
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同步时钟驱动就是加上个时钟信号clk
我只会写成两个文件的方式,用testbench来生成激励,代码如下(具体没有仿真过,那个initial中的仿真时间可以自己调一下)
分两个模块写,自己试试看
模块一:
module AAAA (clk,add, sub, rst, Fn);
input clk,add, sub, rst;
output Fn;
reg [7:0] Fn;
always @ (posedge clk)
begin
if (rst)
Fn <= 0;
else if (add)
Fn <= Fn + 8'd1;
else if (sub)
Fn <= Fn - 8'd1;
else
Fn <= Fn;
end
endmodule
模块二(即测试激励模块)
`timescale 1ns/100ps
module tb_AAA;
reg [7:0] Fn;
wire clk,add,sub,rst;
AAAA inst_AAA(
.clk(clk),
.add(add),
.sub(sub),
.rst(rst),
.Fn(Fn)
);
initial begin
clk = 0;
add = 0;
sub = 0;
rst = 0;
#100 rst = 1;
#150 rst = 0;
#200 add = 1;
#1000 add = 0;
#100 sub = 1;
end
always #50 clk = ~clk;
endmodule |
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