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编码器输出2路相差90°的脉冲，现需要8分频输出，在电机不停地正反转下相位关系要对
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(
clk_a:in std_logic; --A信号
clk_b:in std_logic; --B信号
out_a : out STD_LOGIC; --八分频输出
out_b : out STD_LOGIC; --八分频输出
k : out STD_LOGIC --输出相位关系
);
end fenpin;
architecture arch of fenpin is
signal count_a :std_logic_vector(2 downto 0):="000";
signal count_b :std_logic_vector(2 downto 0):="000";
signal kout:std_logic:='1';
begin
k<=kout;
process(clk_a,kout)
begin
if (kout'event) then count_a<="000";count_b<="000";--电机转向变化时清除计数
else
if (clk_a'event and clk_a='1')
then
if (count_a="111") then
count_a<=(others=>'0');
else
count_a<=count_a+1;
if(count_a(2)='0') then
out_a<='1';
else
out_a<='0';
end if;
end if;
end if;
end if;
end process;
-- a信号八分频
process(clk_b,kout)
begin
if (kout'event ) then count_a<="000";count_b<="000";--电机转向变化时清除计数
else
if (clk_b'event and clk_b='1')
then
if (count_b="111") then
count_b<=(others=>'0');
else
count_b<=count_b+1;
if(count_b(2)='0') then
out_b<='1';
else
out_b<='0';
end if;
end if;
end if;
end if;
end process;
-- b信号八分频
process(clk_a,clk_b)
begin
if (clk_a'event and clk_a='1') then
if clk_b='1' then
kout<='1';
else
kout<='0';
end if;
end if;
end process;
-- ab信号相位判断
end arch; |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2011-7-22 16:29:06
楼主
