模块调用问题，高手请进

yigeren0405

小弟想在always语句中实现模块调用，写了一小段程序如下：
always@(posedge clk)
begin
        cnt_p<=cnt_p+15'b1;
        if(cnt_p<=1000)
        begin
                cnt_p<=0;
                clk_div #(20) U1(.clk(clk),.cout(be;;));
        end
end
编译时，提示有错：
Error (10170): Verilog HDL syntax error at bell.v(15) near text "#";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at bell.v(15) near text ".";  expecting ")", or ",", or an identifier, or a number, or a system task, or "(", or "{", or unary operator,
是不是调用有问题？还是在always语句中不能调用模块？
知道的情赐教，谢谢了