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发表于 2011-5-31 23:21:29
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this approach depends critically on the leakage current, both from the capacitor and from the io pin - leakage increases the time it takes to charge up the capacitor, thus inflate its reading. you can simulate its impact by paralleling a high value resistor to the capacitor.
to null it, your ccs has to generate a current significantly larger than the leakage - this limits its usable range.
your ccs is pretty good. its downside is likely linearity (which depends on the gain and voltage drop over the ccs), and thermal stability.
to increase gain, you can use an ic based solution. for example, you can use a tl431 in place of Q2. this helps with thermal stability as well.
to alleviate the voltage drop issue, you can use a current transfer circuit (aka a current mirror) to isolate the control side from the charge-up side. |
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