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一下是FPGA串口发送程序,上位机接收的数据位发送的2倍,也就是说发送的数据向高位移了1位。我看了硬件应该没问题,请问这程序哪里出了错?
时钟:50MHZ
顶层文件 transfer.vhd
library ieee;
use ieee.std_logic_1164.all;
entity transfer is
port(clk,reset,start : in std_logic;
txd,txddone : out std_logic);
end transfer;
architecture behave of transfer is
component baud
port(clk,resetb : in std_logic;
bclk : out std_logic);
end component;
component txmit
port(bclkt,resett,xmit_cmd_p : in std_logic;
txd,txd_done : out std_logic);
end component;
signal bclk:std_logic;
begin
U1:baud port map ( clk , reset , bclk );
U2:txmit port map ( bclk, reset , start , txd, txddone );
end behave;
波特率发生器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity baud is
Port (clk,resetb:in std_logic;
bclk:out std_logic);
end baud;
architecture Behavioral of baud is
begin
process(clk,resetb)
variable cnt:integer;
begin
if resetb='0' then cnt:=0; bclk<='0'; --复位
elsif rising_edge(clk) then
if cnt>=325 then cnt:=0; bclk<='1'; --设置分频系数
else cnt:=cnt+1; bclk<='0';
end if;
end if;
end process;
end Behavioral;
有限状态机实现发送逻辑
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity txmit is
generic(framlent:integer:=8);
Port (bclkt,resett,xmit_cmd_p:in std_logic; --定义输入输出信号
txdbuf:in std_logic_vector(7 downto 0):="10011011";
txd:out std_logic;
txd_done:out std_logic);
end txmit;
architecture Behavioral of txmit is
type states is (x_idle,x_start,x_wait,x_shift,x_stop); --定义个子状态
signal state:states:=x_idle;
signal tcnt:integer:=0;
begin
process(bclkt,resett,xmit_cmd_p,txdbuf) --主控时序、组合进程
variable xcnt16:std_logic_vector(4 downto 0):="00000"; --定义中间变量
variable xbitcnt:integer:=0;
variable txds:std_logic;
begin
if resett='0' then state<=x_idle; txd_done<='0'; txds:='1'; --复位
elsif rising_edge(bclkt) then
case state is
when x_idle=> --状态1,等待数据帧发送命令
if xmit_cmd_p='0' then state<=x_start; txd_done<='0';
else state<=x_idle;
end if;
when x_start=> --状态2,发送信号至起始位
if xcnt16>="01111" then state<=x_wait; xcnt16:="00000";
else xcnt16:=xcnt16+1; txds:='0'; state<=x_start;
end if;
when x_wait=> --状态3,等待状态
if xcnt16>="01110" then
if xbitcnt=framlent then state<=x_stop; xbitcnt:=0;
else state<=x_shift;
end if;
xcnt16:="00000";
else xcnt16:=xcnt16+1; state<=x_wait;
end if;
when x_shift=>txds:=txdbuf(xbitcnt); xbitcnt:=xbitcnt+1; state<=x_wait; --状态4,将待发数据进行并串转换
when x_stop=> --状态5,停止位发送状态
if xcnt16>="01111" then
if xmit_cmd_p='1' then state<=x_idle; xcnt16:="00000";
else xcnt16:=xcnt16; state<=x_stop;
end if; txd_done<='1';
else xcnt16:=xcnt16+1; txds:='1'; state<=x_stop;
end if;
when others=>state<=x_idle;
end case;
end if;
txd<=txds;
end process;
end Behavioral; |
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