QUARTUS9.0与QUARTUS5.0 VHDL 菜鸟求教

caicaidabing

我这段程序是用来提取IRIG-B码的,就是测量B码高电平的宽度,转换成1或者0,用5.0版本的时候可以正确编译,调试也正确,用9.0版本编译的时候出问题.同一个进程不能有多个时钟上升沿的问题,我改了之后还是不行
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tiqu is
port(rst:in std_logic;--b码解码的复位信号
     clk_50mh:in std_logic;--基准时钟
     b:in std_logic;--b码
     b_good:out std_logic;
    -- PPSOUT,PPMOUT,PPHOUT,S1OUT,S2OUT,BOUT:out std_logic;
     second_l,second_h,minute_l,minute_h,hour_l,hour_h:out std_logic_vector(7 downto 0);
     day_l,day,day_h:out std_logic_vector(7 downto 0);
     nianl_l,nianl_h:out std_logic_vector(7 downto 0));  --
end tiqu;

architecture one of tiqu is
signal cnt0,cnt,cnt1,cnt2:integer range 0 to 7999;
signal sl: std_logic_vector(3 downto 0);
signal sh: std_logic_vector(3 downto 0);
signal ml: std_logic_vector(3 downto 0);
signal mh: std_logic_vector(3 downto 0);
signal hl: std_logic_vector(3 downto 0);
signal hh: std_logic_vector(3 downto 0);
signal dl: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
signal dh: std_logic_vector(3 downto 0);
signal nll: std_logic_vector(3 downto 0);
signal nlh: std_logic_vector(3 downto 0);
signal b_next:std_logic;
type states is(s01,s02,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,
               s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s40,s41,s42,s43,s44,s45,s46,s47,s48,
               s49,s50,s51,s52,s53,s54,s55,s56,s57,s58);
signal current_state,next_state:states;
signal clk:std_logic;
begin
u1:process(clk_50mh)--分频为1MHz
     constant counter_len:integer:=49;
     variable cnt:integer range 0 to counter_len;
    begin
     if clk_50mh'event and clk_50mh='1' then
       if cnt=counter_len then
          cnt:=0;
       else
          cnt:=cnt+1;
       end if;
       case cnt is
         when 0 to counter_len/2=>clk<='0';
         when others            =>clk<='1';
       end case;
     end if;
end process u1;
u2:process(rst,b)--b码解码                  
begin
if rst='1' then
   current_state<=s01;
elsif (b'event and b= '1') then
    current_state <= next_state;
  end if;
end process u2;

u3:process(clk,b,cnt1,cnt2,current_state,b_next)
begin
case current_state is
when s01=>if b='0' then --检测码头
             cnt1<=0;
          elsif clk'event and clk='1' then           ------66
            cnt1<=cnt1+1;b_next<=b;
          end if;
          if b='0' and b_next='1' then
          cnt2<=cnt1;
          end if;
          if cnt2>7000 then
            next_state<=s02;
          else next_state<=s01;
          end if;
when s02=>if b='0' then
             cnt1<=0;
          elsif clk'event and clk='1' then                --78
            cnt1<=cnt1+1;
          end if;
        if b='0' and b_next='1' then
          cnt2<=cnt1;
          end if;
          if cnt2>7000 then
            next_state<=s1;b_good<='1';
          else next_state<=s01;
          end if;
when s1 =>if b='0' then --秒
             cnt1<=0;
          elsif clk'event and clk='1' then          -------90
            cnt1<=cnt1+1;
          end if;
          if b='0' and b_next='1' then
          cnt2<=cnt1;
          end if;
          if cnt2>4000 and cnt2<6000 then
            sl(0)<='1';
          else sl(0)<='0';
          end if;
       next_state<=s2;
when s2=>if b='0' then
             cnt1<=0;
          elsif clk'event and clk='1' then      ----------103
            cnt1<=cnt1+1;
          end if;
          if b='0' and b_next='1' then
          cnt2<=cnt1;
         end if;
         if cnt2>4000 and cnt2<6000 then
            sl(1)<='1';
         else sl(1)<='0';
         end if;
        next_state<=s3;
when s3=>if b='0' then
             cnt1<=0;
          elsif clk'event and clk='1' then             ---------
            cnt1<=cnt1+1;
          end if;
          if b='0' and b_next='1' then
          cnt2<=cnt1;
         end if;
         if cnt2>4000 and cnt2<6000 then
            sl(2)<='1';
         else sl(2)<='0';
         end if;
      next_state<=s4;
when s4=>if b='0' then
             cnt1<=0;
          elsif clk'event and clk='1' then   -----------------
            cnt1<=cnt1+1;
          end if;
         if b='0' and b_next='1' then
          cnt2<=cnt1;
         end if;
         if cnt2>4000 and cnt2<6000 then
            sl(3)<='1';
         else sl(3)<='0';
         end if;
       next_state<=s5;
     
--中间省去格式相同的----

when s58=>if b='0' then
             cnt1<=0;
          elsif clk'event and clk='1' then             ---------
            cnt1<=cnt1+1;
          end if;
        if b='0' and b_next='1' then
          cnt2<=cnt1;
         end if;
         if cnt2>4000 and cnt2<6000 then
            nlh(3)<='1';
         else nlh(3)<='0';
         end if;
        next_state<=s01;
end case;
sh(3)<='0';
mh(3)<='0';
hh(2)<='0';
hh(3)<='0';
dh(2)<='0';
dh(3)<='0';
second_l<="0000" & sl;
second_h<="0000" & sh;
minute_l<="0000" & ml;
minute_h<="0000" & mh;
hour_l<="0000" & hl;
hour_h<="0000" & hh;
day_l<="0000" & dl;
day<="0000" & d;
day_h<="0000" & dh;
nianl_l<="0000" & nll;
nianl_h<="0000" & nlh;
end process u3;
end one;

Error (10822): HDL error at tiqu.vhd(66): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(78): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(90): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(103): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(116): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(129): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(143): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(156): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(169): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(183): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(196): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(209): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(222): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(236): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(249): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(262): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(277): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(290): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at tiqu.vhd(303): couldn't implement registers for assignments on this clock edge