入门问题一个，双向IO相关[楼主上火了]

qingqng

毕设相关，stm32的fsmc总线通过cpld访问tft，I8080模式
新手刚接触cpld若干小时，对io口状态不怎么理解
2条16bit数据总线，查了查资料，大体上和下面程序差不多

我在读总线inputdata的时候，是否需要程序设置输入高阻，还是编译之后IO状态逻辑由quartus自动完成了？一般mcu都是要自己动手的，编译器也不支持这么搞。。。。
同理，用双向io输出的时候是否可以直接这样OUTPUTDADA<=INPUTDADA，而不需要设置输出模式?quartus威武啊
但是这种转换应该需要若干ns的时间吧？
问题有点杂乱，思路大概清晰。。。因为样板还没到，只好求助



附：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
---------TOP LEVEL ENTITY---------
ENTITY CPLD IS
PORT
(

CLK:IN STD_LOGIC;
----------LEDS------------
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--------SDRAMIO-----------
signal sdram_clk : OUT STD_LOGIC;
signal sdram_cke : OUT STD_LOGIC;     
signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal sdram_cs_n : OUT STD_LOGIC;
signal sdram_ras_n : OUT STD_LOGIC;
signal sdram_cas_n : OUT STD_LOGIC;
signal sdram_we_n : OUT STD_LOGIC;
signal sdram_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-------CONNECTS2FSMC-------
FSMCNOE:IN STD_LOGIC;
FSMCNWE:IN STD_LOGIC;
FSMCNE:IN STD_LOGIC;
STMIO1:INOUT STD_LOGIC;
STMIO2:INOUT STD_LOGIC;
FSMCADDR0:IN STD_LOGIC;
FSMCADDR1:IN STD_LOGIC;
FSMCADDR2:IN STD_LOGIC;
FSMCDATA:INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

-------OUTIOS--------------
OUTCS:OUT STD_LOGIC;
OUTRS:OUT STD_LOGIC;
OUTRW:OUT STD_LOGIC;
OUTRD:OUT STD_LOGIC;
OUTRT:OUT STD_LOGIC;
OUTM3:OUT STD_LOGIC;
OUTM0:OUT STD_LOGIC;
OUTDATA:INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END;

----------
ARCHITECTURE behave OF CPLD IS
SIGNAL DATAIN:STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL DATAOUT:STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
OUTRT    <= '1';
OUTM3    <= '1';
OUTM0    <= '0';
PROCESS (FSMCNE,FSMCNWE)
BEGIN
-----------if CS---------------------
IF (FSMCNE='0') THEN
-----------if RW--------------------
IF (FSMCNWE='0') THEN
FSMCDATA  <=OUTDATA;
ELSE ---------if nRW-----------------
OUTDATA   <=FSMCDATA;
END IF;
--------------output follow------------
OUTCS    <=FSMCNE;
OUTRS    <= FSMCADDR0;
OUTRW    <= FSMCNWE;
OUTRD    <= FSMCNOE;

ELSE
FSMCDATA <="ZZZZZZZZZZZZZZZZ";
OUTDATA  <="ZZZZZZZZZZZZZZZZ";
OUTCS   <='Z';
OUTRS   <='Z';
OUTRW   <='Z';
OUTRD   <='Z';
END IF;
END PROCESS;
END;


IO输入输出状态转化的时间是否需要在stm32访问tft的时候额外设置延时？比如dataset time相应增加1之类。。
NE/CS之前数据口保持高阻输入。。。这样子真的没问题嘛
手头没东西，干上火。。。

qingqng

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
---------TOP LEVEL ENTITY---------
ENTITY CPLD IS
PORT
(

CLK:IN STD_LOGIC;
----------LEDS------------
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--------SDRAMIO-----------
signal sdram_clk : OUT STD_LOGIC;
signal sdram_cke : OUT STD_LOGIC;     
signal sdram_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sdram_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal sdram_cs_n : OUT STD_LOGIC;
signal sdram_ras_n : OUT STD_LOGIC;
signal sdram_cas_n : OUT STD_LOGIC;
signal sdram_we_n : OUT STD_LOGIC;
signal sdram_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-------CONNECTS2FSMC-------
FSMCNOE:IN STD_LOGIC;
FSMCNWE:IN STD_LOGIC;
FSMCNE:IN STD_LOGIC;
STMIO1:INOUT STD_LOGIC;
STMIO2:INOUT STD_LOGIC;
FSMCADDR0:IN STD_LOGIC;
FSMCADDR1:IN STD_LOGIC;
FSMCADDR2:IN STD_LOGIC;
FSMCDATA:INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

-------OUTIOS--------------
OUTCS:OUT STD_LOGIC;
OUTRS:OUT STD_LOGIC;
OUTRW:OUT STD_LOGIC;
OUTRD:OUT STD_LOGIC;
OUTRT:OUT STD_LOGIC;
OUTM3:OUT STD_LOGIC;
OUTM0:OUT STD_LOGIC;
OUTDATA:INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END;

----------
ARCHITECTURE behave OF CPLD IS
SIGNAL DATACI:STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL DATACO:STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
OUTRT    <= '1';
OUTM3    <= '1';
OUTM0    <= '0';
OUTCS    <=FSMCNE;
OUTRS    <= FSMCADDR0;
OUTRW    <= FSMCNWE;
OUTRD    <= FSMCNOE;
PROCESS (FSMCDATA,FSMCNE,FSMCNWE)
BEGIN
-----------if CS
IF (FSMCNE='0') THEN
-----------if RW
IF (FSMCNWE='0') THEN
DATACO   <=FSMCDATA;
ELSE ---------if nRW
DATACO   <="ZZZZZZZZZZZZZZZZ";
END IF;
END IF;
OUTDATA <=DATACO;
END PROCESS;
----------------------------------------------------------------
PROCESS (OUTDATA,FSMCNE,FSMCNWE)
BEGIN
-----------if CS
IF (FSMCNE='0') THEN
-----------if RW------------
IF (FSMCNWE='0') THEN
DATACI   <=OUTDATA;
ELSE
DATACI   <="ZZZZZZZZZZZZZZZZ";
END IF;
END IF;
FSMCDATA <=DATACI;
END PROCESS;

END;