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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
songa : in std_logic;
songb : in std_logic;
songc : in std_logic;
Circle : in std_logic;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSICFORTH --音符数据ROM
PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);--INTEGER RANGE 512 DOWNTO 0;
BEGIN
CNT8 : PROCESS(clk, songa,songb,songc,Circle,Counter)
--VARIABLE Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);--INTEGER RANGE 512 DOWNTO 0;
BEGIN
IF Circle='0' then (显示这部分出错 )
IF (songa='1') and (songb='0') and (songc='0') then--FOR Counter IN 0 TO 138 LOOP
IF (Counter>=138) THEN Counter <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
Counter <= Counter+1;
END IF;-- END IF;
ELSIF (songa='0') and (songb='1') and (songc='0') then
IF (Counter<=144) or (Counter>=209) then Counter <= "10010000";
ELSIF (clk'EVENT AND clk = '1') THEN
--Counter <= Counter+1;
END IF;-- END IF;
ELSIF (songa='0') and (songb='0') and (songc='1') then A
IF (Counter<=216) then Counter<= "11011000";
ELSIF (clk'EVENT AND clk = '1') THEN
Counter <= Counter+1;
END IF;-- END IF;
ELSE NULL;--ELSE Counter<= "00000000";--NULL;
END IF;
ELSIF Circle='1' then
IF Counter>=423 then Counter<= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
Counter <= Counter+1;
END IF;
--END IF;--
ELSE NULL;
END IF;
END PROCESS;
u1 : MUSICFORTH PORT MAP(address=>Counter, q=>ToneIndex, clock=>clk);
END;
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[0]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[1]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[2]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[3]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[4]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[5]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[6]" because its behavior does not match any supported register model
Error (10821): HDL error at NoteTabs.vhd(33): can't infer register for "Counter[7]" because its behavior does not match any supported register model
Error (10822): HDL error at NoteTabs.vhd(35): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at NoteTabs.vhd(47): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate user hierarchy "NoteTabs:u1"
Error: Quartus II Analysis & Synthesis was unsuccessful. 11 errors, 0 warnings
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 0 warnings
课程设计要求播放三首歌,去掉Counter<=Counter+1 就编译成功,rom是512字节,不连续地放了三首歌,共占四百多字节,不知道是不是与rom有关,因为听说std_logic_vector 只能累加到255.又可能是if then 条件设置有错,不知道怎么改 很疑惑。请各位指教。
另外 用的是quartus2 的7.2软件 用了个cra_ck破_解了一下 发现不可以使用任何devices 请各位指教 |
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知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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