modelsim仿真出错了

smart060401

(原文件名:untitled.JPG)
这是quartus中的block图，我把它转为verilog在modelsim中仿真，结果却不对，如下图所示

(原文件名:untitled2.JPG)


但是我自己写的verilog程序dff_3仿真就正确
module dff_3(in,clk,reset,out,cd);
input in;
input clk;
input reset;
output out;
reg out;
output reg cd;
reg out1;
always @(posedge clk or negedge reset)
  if(!reset)
    begin
      out1<=0;
      cd<=0;
      out<=0;
  end
else
    begin
     out1<=in;
      cd<=out1;
      out<=cd;
    end
endmodule
这是quartus转的verilog代码
// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors.  Please refer to the
// applicable agreement for further details.
// PROGRAM  "Quartus II"
// VERSION  "Version 9.1 Build 222 10/21/2009 SJ Full Version"
// CREATED  "Tue Mar 08 17:59:23 2011"
module gg(
in,
clk,
reset,
out,
cd
);

input in;
input clk;
input reset;
output out;
reg out;
output cd;
reg cd_ALTERA_SYNTHESIZED;
reg DFF_inst;


always@(posedge clk or negedge reset)
begin
if (!reset)
begin
DFF_inst = 0;
end
else
begin
DFF_inst = in;
end
end

always@(posedge clk or negedge reset)
begin
if (!reset)
begin
cd_ALTERA_SYNTHESIZED = 0;
end
else
begin
cd_ALTERA_SYNTHESIZED = DFF_inst;
end
end

always@(posedge clk or negedge reset)
begin
if (!reset)
begin
out = 0;
end
else
begin
out = cd_ALTERA_SYNTHESIZED;
end
end
assign cd = cd_ALTERA_SYNTHESIZED;
endmodule
没看出quartus转的verilog有什么问题啊。。