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`timescale 1ns/1ns
module key( clk ,rst, key,led);
input clk;
input rst;
input key;
output led;
wire hhreg;
wire llreg;
keyscan u1 (
.clk(clk),
.rst(rst),
.key1(key),
.hhreg(hhreg),
.llreg(llreg)
);
keyout u2 (
.clk(clk),
.rst(rst),
.hhreg(hhreg),
.llreg(llreg),
.led(led)
);
endmodule
module keyscan ( clk ,rst,key1 ,hhreg,llreg);
input clk;
input rst;
input key1;
//output led;
output hhreg;
output llreg;
parameter t1ms=16'd19_999;
reg [15:0] count;
reg h2hreg;
reg h2lreg;
reg l2hreg;
reg l2lreg;
reg isen;
always @(posedge clk or negedge rst )
if(!rst)
begin
isen <=1'b0;
count<=16'd0;
end
else if(count==t1ms)
begin
isen <=1'b1;
end
else
begin
count<=count +1'b1;
end
always @(posedge clk or negedge rst )
if(!rst)
begin
h2hreg <=1'b1;
h2lreg <=1'b1;
l2hreg <=1'b0;
l2lreg <=1'b0;
end
else
begin
h2hreg <=key1;
h2lreg <=h2hreg;
l2hreg <=key1;
l2lreg <=l2hreg;
end
assign hhreg = isen? (h2hreg&!h2lreg):1'b0;
assign llreg = isen? (!l2hreg&l2lreg):1'b0;
endmodule
//*********************************************************
module keyout ( clk ,rst ,hhreg,llreg,led);
input clk;
input rst;
input hhreg;
input llreg;
output led;
parameter t20ms=20'hfffff;
reg [19:0] count; //20ms
reg led1;
//reg led1;
reg [1:0] i;
always @(posedge clk or negedge rst )
if(!rst)
begin
count<=20'd0;
end
else
begin
count<=count +1'b1;
end
always @(posedge clk or negedge rst )
if(!rst)
begin
i<=2'd0;
count<=20'd0;
end
else if(count==t20ms)
begin
case (i)
2'd0:
begin
if(hhreg) i<=2'd1;
else if(llreg) i<=2'd2;
end
2'd1:
begin
led1<=1'b0;
i<=2'd0;
end
2'd2:
begin
led1<=1'b1;
i<=2'd0;
end
endcase
end
assign led=led1;
endmodule |
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知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2010-12-19 16:14:01
楼主